15d8a437cSNishad Kamdar /* SPDX-License-Identifier: BSD-3-Clause */ 2aa276781SNishanth Menon /* 3aa276781SNishanth Menon * Texas Instruments System Control Interface (TISCI) Protocol 4aa276781SNishanth Menon * 5aa276781SNishanth Menon * Communication protocol with TI SCI hardware 6aa276781SNishanth Menon * The system works in a message response protocol 7aa276781SNishanth Menon * See: http://processors.wiki.ti.com/index.php/TISCI for details 8aa276781SNishanth Menon * 9a6df49f4SAlexander A. Klimov * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ 10aa276781SNishanth Menon */ 11aa276781SNishanth Menon 12aa276781SNishanth Menon #ifndef __TI_SCI_H 13aa276781SNishanth Menon #define __TI_SCI_H 14aa276781SNishanth Menon 15aa276781SNishanth Menon /* Generic Messages */ 16aa276781SNishanth Menon #define TI_SCI_MSG_ENABLE_WDT 0x0000 17aa276781SNishanth Menon #define TI_SCI_MSG_WAKE_RESET 0x0001 18aa276781SNishanth Menon #define TI_SCI_MSG_VERSION 0x0002 19aa276781SNishanth Menon #define TI_SCI_MSG_WAKE_REASON 0x0003 20aa276781SNishanth Menon #define TI_SCI_MSG_GOODBYE 0x0004 21912cffb4SNishanth Menon #define TI_SCI_MSG_SYS_RESET 0x0005 22aa276781SNishanth Menon 239e7d756dSNishanth Menon /* Device requests */ 249e7d756dSNishanth Menon #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 259e7d756dSNishanth Menon #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 269e7d756dSNishanth Menon #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 279e7d756dSNishanth Menon 289f723220SNishanth Menon /* Clock requests */ 299f723220SNishanth Menon #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 309f723220SNishanth Menon #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 319f723220SNishanth Menon #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 329f723220SNishanth Menon #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 339f723220SNishanth Menon #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 349f723220SNishanth Menon #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 359f723220SNishanth Menon #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 369f723220SNishanth Menon #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 379f723220SNishanth Menon 389c19fb68SLokesh Vutla /* Resource Management Requests */ 399c19fb68SLokesh Vutla #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 409c19fb68SLokesh Vutla 41997b001fSLokesh Vutla /* IRQ requests */ 42997b001fSLokesh Vutla #define TI_SCI_MSG_SET_IRQ 0x1000 43997b001fSLokesh Vutla #define TI_SCI_MSG_FREE_IRQ 0x1001 44997b001fSLokesh Vutla 4568608b5eSPeter Ujfalusi /* NAVSS resource management */ 4668608b5eSPeter Ujfalusi /* Ringacc requests */ 4768608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100 4868608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_RING_FREE 0x1101 4968608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 5068608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_RING_RESET 0x1103 5168608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_RING_CFG 0x1110 5268608b5eSPeter Ujfalusi 5368608b5eSPeter Ujfalusi /* PSI-L requests */ 5468608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 5568608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 5668608b5eSPeter Ujfalusi 5768608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 5868608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 5968608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 6068608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 6168608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 6268608b5eSPeter Ujfalusi #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 6368608b5eSPeter Ujfalusi 6468608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 6568608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206 6668608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 6768608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216 6868608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 6968608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 7068608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232 7168608b5eSPeter Ujfalusi #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233 7268608b5eSPeter Ujfalusi 731e407f33SSuman Anna /* Processor Control requests */ 741e407f33SSuman Anna #define TI_SCI_MSG_PROC_REQUEST 0xc000 751e407f33SSuman Anna #define TI_SCI_MSG_PROC_RELEASE 0xc001 761e407f33SSuman Anna #define TI_SCI_MSG_PROC_HANDOVER 0xc005 771e407f33SSuman Anna #define TI_SCI_MSG_SET_CONFIG 0xc100 781e407f33SSuman Anna #define TI_SCI_MSG_SET_CTRL 0xc101 791e407f33SSuman Anna #define TI_SCI_MSG_GET_STATUS 0xc400 801e407f33SSuman Anna 81aa276781SNishanth Menon /** 82aa276781SNishanth Menon * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 83aa276781SNishanth Menon * @type: Type of messages: One of TI_SCI_MSG* values 84aa276781SNishanth Menon * @host: Host of the message 85aa276781SNishanth Menon * @seq: Message identifier indicating a transfer sequence 86aa276781SNishanth Menon * @flags: Flag for the message 87aa276781SNishanth Menon */ 88aa276781SNishanth Menon struct ti_sci_msg_hdr { 89aa276781SNishanth Menon u16 type; 90aa276781SNishanth Menon u8 host; 91aa276781SNishanth Menon u8 seq; 92aa276781SNishanth Menon #define TI_SCI_MSG_FLAG(val) (1 << (val)) 93aa276781SNishanth Menon #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 94aa276781SNishanth Menon #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 95aa276781SNishanth Menon #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 96aa276781SNishanth Menon #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 97aa276781SNishanth Menon #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 98aa276781SNishanth Menon /* Additional Flags */ 99aa276781SNishanth Menon u32 flags; 100aa276781SNishanth Menon } __packed; 101aa276781SNishanth Menon 102aa276781SNishanth Menon /** 103aa276781SNishanth Menon * struct ti_sci_msg_resp_version - Response for a message 104aa276781SNishanth Menon * @hdr: Generic header 105aa276781SNishanth Menon * @firmware_description: String describing the firmware 106aa276781SNishanth Menon * @firmware_revision: Firmware revision 107aa276781SNishanth Menon * @abi_major: Major version of the ABI that firmware supports 108aa276781SNishanth Menon * @abi_minor: Minor version of the ABI that firmware supports 109aa276781SNishanth Menon * 110aa276781SNishanth Menon * In general, ABI version changes follow the rule that minor version increments 111aa276781SNishanth Menon * are backward compatible. Major revision changes in ABI may not be 112aa276781SNishanth Menon * backward compatible. 113aa276781SNishanth Menon * 114aa276781SNishanth Menon * Response to a generic message with message type TI_SCI_MSG_VERSION 115aa276781SNishanth Menon */ 116aa276781SNishanth Menon struct ti_sci_msg_resp_version { 117aa276781SNishanth Menon struct ti_sci_msg_hdr hdr; 118aa276781SNishanth Menon char firmware_description[32]; 119aa276781SNishanth Menon u16 firmware_revision; 120aa276781SNishanth Menon u8 abi_major; 121aa276781SNishanth Menon u8 abi_minor; 122aa276781SNishanth Menon } __packed; 123aa276781SNishanth Menon 1249e7d756dSNishanth Menon /** 125912cffb4SNishanth Menon * struct ti_sci_msg_req_reboot - Reboot the SoC 126912cffb4SNishanth Menon * @hdr: Generic Header 127912cffb4SNishanth Menon * 128912cffb4SNishanth Menon * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 129912cffb4SNishanth Menon * ACK/NACK message. 130912cffb4SNishanth Menon */ 131912cffb4SNishanth Menon struct ti_sci_msg_req_reboot { 132912cffb4SNishanth Menon struct ti_sci_msg_hdr hdr; 133912cffb4SNishanth Menon } __packed; 134912cffb4SNishanth Menon 135912cffb4SNishanth Menon /** 1369e7d756dSNishanth Menon * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 1379e7d756dSNishanth Menon * @hdr: Generic header 1389e7d756dSNishanth Menon * @id: Indicates which device to modify 1399e7d756dSNishanth Menon * @reserved: Reserved space in message, must be 0 for backward compatibility 1409e7d756dSNishanth Menon * @state: The desired state of the device. 1419e7d756dSNishanth Menon * 1429e7d756dSNishanth Menon * Certain flags can also be set to alter the device state: 1439e7d756dSNishanth Menon * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 1449e7d756dSNishanth Menon * The meaning of this flag will vary slightly from device to device and from 1459e7d756dSNishanth Menon * SoC to SoC but it generally allows the device to wake the SoC out of deep 1469e7d756dSNishanth Menon * suspend states. 1479e7d756dSNishanth Menon * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 1489e7d756dSNishanth Menon * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 1499e7d756dSNishanth Menon * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 1509e7d756dSNishanth Menon * If another host already has this device set to STATE_RETENTION or STATE_ON, 1519e7d756dSNishanth Menon * the message will fail. Once successful, other hosts attempting to set 1529e7d756dSNishanth Menon * STATE_RETENTION or STATE_ON will fail. 1539e7d756dSNishanth Menon * 1549e7d756dSNishanth Menon * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 1559e7d756dSNishanth Menon * ACK/NACK message. 1569e7d756dSNishanth Menon */ 1579e7d756dSNishanth Menon struct ti_sci_msg_req_set_device_state { 1589e7d756dSNishanth Menon /* Additional hdr->flags options */ 1599e7d756dSNishanth Menon #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 1609e7d756dSNishanth Menon #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 1619e7d756dSNishanth Menon #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 1629e7d756dSNishanth Menon struct ti_sci_msg_hdr hdr; 1639e7d756dSNishanth Menon u32 id; 1649e7d756dSNishanth Menon u32 reserved; 1659e7d756dSNishanth Menon 1669e7d756dSNishanth Menon #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 1679e7d756dSNishanth Menon #define MSG_DEVICE_SW_STATE_RETENTION 1 1689e7d756dSNishanth Menon #define MSG_DEVICE_SW_STATE_ON 2 1699e7d756dSNishanth Menon u8 state; 1709e7d756dSNishanth Menon } __packed; 1719e7d756dSNishanth Menon 1729e7d756dSNishanth Menon /** 1739e7d756dSNishanth Menon * struct ti_sci_msg_req_get_device_state - Request to get device. 1749e7d756dSNishanth Menon * @hdr: Generic header 1759e7d756dSNishanth Menon * @id: Device Identifier 1769e7d756dSNishanth Menon * 1779e7d756dSNishanth Menon * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 1789e7d756dSNishanth Menon * information 1799e7d756dSNishanth Menon */ 1809e7d756dSNishanth Menon struct ti_sci_msg_req_get_device_state { 1819e7d756dSNishanth Menon struct ti_sci_msg_hdr hdr; 1829e7d756dSNishanth Menon u32 id; 1839e7d756dSNishanth Menon } __packed; 1849e7d756dSNishanth Menon 1859e7d756dSNishanth Menon /** 1869e7d756dSNishanth Menon * struct ti_sci_msg_resp_get_device_state - Response to get device request. 1879e7d756dSNishanth Menon * @hdr: Generic header 1889e7d756dSNishanth Menon * @context_loss_count: Indicates how many times the device has lost context. A 1899e7d756dSNishanth Menon * driver can use this monotonic counter to determine if the device has 1909e7d756dSNishanth Menon * lost context since the last time this message was exchanged. 1919e7d756dSNishanth Menon * @resets: Programmed state of the reset lines. 1929e7d756dSNishanth Menon * @programmed_state: The state as programmed by set_device. 1939e7d756dSNishanth Menon * - Uses the MSG_DEVICE_SW_* macros 1949e7d756dSNishanth Menon * @current_state: The actual state of the hardware. 1959e7d756dSNishanth Menon * 1969e7d756dSNishanth Menon * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 1979e7d756dSNishanth Menon */ 1989e7d756dSNishanth Menon struct ti_sci_msg_resp_get_device_state { 1999e7d756dSNishanth Menon struct ti_sci_msg_hdr hdr; 2009e7d756dSNishanth Menon u32 context_loss_count; 2019e7d756dSNishanth Menon u32 resets; 2029e7d756dSNishanth Menon u8 programmed_state; 2039e7d756dSNishanth Menon #define MSG_DEVICE_HW_STATE_OFF 0 2049e7d756dSNishanth Menon #define MSG_DEVICE_HW_STATE_ON 1 2059e7d756dSNishanth Menon #define MSG_DEVICE_HW_STATE_TRANS 2 2069e7d756dSNishanth Menon u8 current_state; 2079e7d756dSNishanth Menon } __packed; 2089e7d756dSNishanth Menon 2099e7d756dSNishanth Menon /** 2109e7d756dSNishanth Menon * struct ti_sci_msg_req_set_device_resets - Set the desired resets 2119e7d756dSNishanth Menon * configuration of the device 2129e7d756dSNishanth Menon * @hdr: Generic header 2139e7d756dSNishanth Menon * @id: Indicates which device to modify 2149e7d756dSNishanth Menon * @resets: A bit field of resets for the device. The meaning, behavior, 2159e7d756dSNishanth Menon * and usage of the reset flags are device specific. 0 for a bit 2169e7d756dSNishanth Menon * indicates releasing the reset represented by that bit while 1 2179e7d756dSNishanth Menon * indicates keeping it held. 2189e7d756dSNishanth Menon * 2199e7d756dSNishanth Menon * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 2209e7d756dSNishanth Menon * ACK/NACK message. 2219e7d756dSNishanth Menon */ 2229e7d756dSNishanth Menon struct ti_sci_msg_req_set_device_resets { 2239e7d756dSNishanth Menon struct ti_sci_msg_hdr hdr; 2249e7d756dSNishanth Menon u32 id; 2259e7d756dSNishanth Menon u32 resets; 2269e7d756dSNishanth Menon } __packed; 2279e7d756dSNishanth Menon 2289f723220SNishanth Menon /** 2299f723220SNishanth Menon * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 2309f723220SNishanth Menon * @hdr: Generic Header, Certain flags can be set specific to the clocks: 2319f723220SNishanth Menon * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 2329f723220SNishanth Menon * via spread spectrum clocking. 2339f723220SNishanth Menon * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 2349f723220SNishanth Menon * frequency to be changed while it is running so long as it 2359f723220SNishanth Menon * is within the min/max limits. 2369f723220SNishanth Menon * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 2379f723220SNishanth Menon * is only applicable to clock inputs on the SoC pseudo-device. 2389f723220SNishanth Menon * @dev_id: Device identifier this request is for 2399f723220SNishanth Menon * @clk_id: Clock identifier for the device for this request. 2409f723220SNishanth Menon * Each device has it's own set of clock inputs. This indexes 24181f4458cSTero Kristo * which clock input to modify. Set to 255 if clock ID is 24281f4458cSTero Kristo * greater than or equal to 255. 2439f723220SNishanth Menon * @request_state: Request the state for the clock to be set to. 2449f723220SNishanth Menon * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 2459f723220SNishanth Menon * it can be disabled, regardless of the state of the device 2469f723220SNishanth Menon * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 2479f723220SNishanth Menon * automatically manage the state of this clock. If the device 2489f723220SNishanth Menon * is enabled, then the clock is enabled. If the device is set 2499f723220SNishanth Menon * to off or retention, then the clock is internally set as not 2509f723220SNishanth Menon * being required by the device.(default) 2519f723220SNishanth Menon * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 2529f723220SNishanth Menon * regardless of the state of the device. 25381f4458cSTero Kristo * @clk_id_32: Clock identifier for the device for this request. 25481f4458cSTero Kristo * Only to be used if the clock ID is greater than or equal to 25581f4458cSTero Kristo * 255. 2569f723220SNishanth Menon * 2579f723220SNishanth Menon * Normally, all required clocks are managed by TISCI entity, this is used 2589f723220SNishanth Menon * only for specific control *IF* required. Auto managed state is 2599f723220SNishanth Menon * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 2609f723220SNishanth Menon * will explicitly control. 2619f723220SNishanth Menon * 2629f723220SNishanth Menon * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 2639f723220SNishanth Menon * ACK or NACK message. 2649f723220SNishanth Menon */ 2659f723220SNishanth Menon struct ti_sci_msg_req_set_clock_state { 2669f723220SNishanth Menon /* Additional hdr->flags options */ 2679f723220SNishanth Menon #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 2689f723220SNishanth Menon #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 2699f723220SNishanth Menon #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 2709f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 2719f723220SNishanth Menon u32 dev_id; 2729f723220SNishanth Menon u8 clk_id; 2739f723220SNishanth Menon #define MSG_CLOCK_SW_STATE_UNREQ 0 2749f723220SNishanth Menon #define MSG_CLOCK_SW_STATE_AUTO 1 2759f723220SNishanth Menon #define MSG_CLOCK_SW_STATE_REQ 2 2769f723220SNishanth Menon u8 request_state; 27781f4458cSTero Kristo u32 clk_id_32; 2789f723220SNishanth Menon } __packed; 2799f723220SNishanth Menon 2809f723220SNishanth Menon /** 2819f723220SNishanth Menon * struct ti_sci_msg_req_get_clock_state - Request for clock state 2829f723220SNishanth Menon * @hdr: Generic Header 2839f723220SNishanth Menon * @dev_id: Device identifier this request is for 2849f723220SNishanth Menon * @clk_id: Clock identifier for the device for this request. 2859f723220SNishanth Menon * Each device has it's own set of clock inputs. This indexes 28681f4458cSTero Kristo * which clock input to get state of. Set to 255 if the clock 28781f4458cSTero Kristo * ID is greater than or equal to 255. 28881f4458cSTero Kristo * @clk_id_32: Clock identifier for the device for the request. 28981f4458cSTero Kristo * Only to be used if the clock ID is greater than or equal to 29081f4458cSTero Kristo * 255. 2919f723220SNishanth Menon * 2929f723220SNishanth Menon * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 2939f723220SNishanth Menon * of the clock 2949f723220SNishanth Menon */ 2959f723220SNishanth Menon struct ti_sci_msg_req_get_clock_state { 2969f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 2979f723220SNishanth Menon u32 dev_id; 2989f723220SNishanth Menon u8 clk_id; 29981f4458cSTero Kristo u32 clk_id_32; 3009f723220SNishanth Menon } __packed; 3019f723220SNishanth Menon 3029f723220SNishanth Menon /** 3039f723220SNishanth Menon * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 3049f723220SNishanth Menon * @hdr: Generic Header 3059f723220SNishanth Menon * @programmed_state: Any programmed state of the clock. This is one of 3069f723220SNishanth Menon * MSG_CLOCK_SW_STATE* values. 3079f723220SNishanth Menon * @current_state: Current state of the clock. This is one of: 3089f723220SNishanth Menon * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 3099f723220SNishanth Menon * MSG_CLOCK_HW_STATE_READY: Clock is ready 3109f723220SNishanth Menon * 3119f723220SNishanth Menon * Response to TI_SCI_MSG_GET_CLOCK_STATE. 3129f723220SNishanth Menon */ 3139f723220SNishanth Menon struct ti_sci_msg_resp_get_clock_state { 3149f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 3159f723220SNishanth Menon u8 programmed_state; 3169f723220SNishanth Menon #define MSG_CLOCK_HW_STATE_NOT_READY 0 3179f723220SNishanth Menon #define MSG_CLOCK_HW_STATE_READY 1 3189f723220SNishanth Menon u8 current_state; 3199f723220SNishanth Menon } __packed; 3209f723220SNishanth Menon 3219f723220SNishanth Menon /** 3229f723220SNishanth Menon * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 3239f723220SNishanth Menon * @hdr: Generic Header 3249f723220SNishanth Menon * @dev_id: Device identifier this request is for 3259f723220SNishanth Menon * @clk_id: Clock identifier for the device for this request. 3269f723220SNishanth Menon * Each device has it's own set of clock inputs. This indexes 32781f4458cSTero Kristo * which clock input to modify. Set to 255 if clock ID is 32881f4458cSTero Kristo * greater than or equal to 255. 3299f723220SNishanth Menon * @parent_id: The new clock parent is selectable by an index via this 33081f4458cSTero Kristo * parameter. Set to 255 if clock ID is greater than or 33181f4458cSTero Kristo * equal to 255. 33281f4458cSTero Kristo * @clk_id_32: Clock identifier if @clk_id field is 255. 33381f4458cSTero Kristo * @parent_id_32: Parent identifier if @parent_id is 255. 3349f723220SNishanth Menon * 3359f723220SNishanth Menon * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 3369f723220SNishanth Menon * ACK / NACK message. 3379f723220SNishanth Menon */ 3389f723220SNishanth Menon struct ti_sci_msg_req_set_clock_parent { 3399f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 3409f723220SNishanth Menon u32 dev_id; 3419f723220SNishanth Menon u8 clk_id; 3429f723220SNishanth Menon u8 parent_id; 34381f4458cSTero Kristo u32 clk_id_32; 34481f4458cSTero Kristo u32 parent_id_32; 3459f723220SNishanth Menon } __packed; 3469f723220SNishanth Menon 3479f723220SNishanth Menon /** 3489f723220SNishanth Menon * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 3499f723220SNishanth Menon * @hdr: Generic Header 3509f723220SNishanth Menon * @dev_id: Device identifier this request is for 3519f723220SNishanth Menon * @clk_id: Clock identifier for the device for this request. 3529f723220SNishanth Menon * Each device has it's own set of clock inputs. This indexes 35381f4458cSTero Kristo * which clock input to get the parent for. If this field 35481f4458cSTero Kristo * contains 255, the actual clock identifier is stored in 35581f4458cSTero Kristo * @clk_id_32. 35681f4458cSTero Kristo * @clk_id_32: Clock identifier if the @clk_id field contains 255. 3579f723220SNishanth Menon * 3589f723220SNishanth Menon * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 3599f723220SNishanth Menon */ 3609f723220SNishanth Menon struct ti_sci_msg_req_get_clock_parent { 3619f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 3629f723220SNishanth Menon u32 dev_id; 3639f723220SNishanth Menon u8 clk_id; 36481f4458cSTero Kristo u32 clk_id_32; 3659f723220SNishanth Menon } __packed; 3669f723220SNishanth Menon 3679f723220SNishanth Menon /** 3689f723220SNishanth Menon * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 3699f723220SNishanth Menon * @hdr: Generic Header 37081f4458cSTero Kristo * @parent_id: The current clock parent. If set to 255, the current parent 37181f4458cSTero Kristo * ID can be found from the @parent_id_32 field. 37281f4458cSTero Kristo * @parent_id_32: Current clock parent if @parent_id field is set to 37381f4458cSTero Kristo * 255. 3749f723220SNishanth Menon * 3759f723220SNishanth Menon * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 3769f723220SNishanth Menon */ 3779f723220SNishanth Menon struct ti_sci_msg_resp_get_clock_parent { 3789f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 3799f723220SNishanth Menon u8 parent_id; 38081f4458cSTero Kristo u32 parent_id_32; 3819f723220SNishanth Menon } __packed; 3829f723220SNishanth Menon 3839f723220SNishanth Menon /** 3849f723220SNishanth Menon * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 3859f723220SNishanth Menon * @hdr: Generic header 3869f723220SNishanth Menon * @dev_id: Device identifier this request is for 38781f4458cSTero Kristo * @clk_id: Clock identifier for the device for this request. Set to 38881f4458cSTero Kristo * 255 if clock ID is greater than or equal to 255. 38981f4458cSTero Kristo * @clk_id_32: Clock identifier if the @clk_id field contains 255. 3909f723220SNishanth Menon * 3919f723220SNishanth Menon * This request provides information about how many clock parent options 3929f723220SNishanth Menon * are available for a given clock to a device. This is typically used 3939f723220SNishanth Menon * for input clocks. 3949f723220SNishanth Menon * 3959f723220SNishanth Menon * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 3969f723220SNishanth Menon * message, or NACK in case of inability to satisfy request. 3979f723220SNishanth Menon */ 3989f723220SNishanth Menon struct ti_sci_msg_req_get_clock_num_parents { 3999f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 4009f723220SNishanth Menon u32 dev_id; 4019f723220SNishanth Menon u8 clk_id; 40281f4458cSTero Kristo u32 clk_id_32; 4039f723220SNishanth Menon } __packed; 4049f723220SNishanth Menon 4059f723220SNishanth Menon /** 4069f723220SNishanth Menon * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 4079f723220SNishanth Menon * @hdr: Generic header 40881f4458cSTero Kristo * @num_parents: Number of clock parents. If set to 255, the actual 40981f4458cSTero Kristo * number of parents is stored into @num_parents_32 41081f4458cSTero Kristo * field instead. 41181f4458cSTero Kristo * @num_parents_32: Number of clock parents if @num_parents field is 41281f4458cSTero Kristo * set to 255. 4139f723220SNishanth Menon * 4149f723220SNishanth Menon * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 4159f723220SNishanth Menon */ 4169f723220SNishanth Menon struct ti_sci_msg_resp_get_clock_num_parents { 4179f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 4189f723220SNishanth Menon u8 num_parents; 41981f4458cSTero Kristo u32 num_parents_32; 4209f723220SNishanth Menon } __packed; 4219f723220SNishanth Menon 4229f723220SNishanth Menon /** 4239f723220SNishanth Menon * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 4249f723220SNishanth Menon * @hdr: Generic Header 4259f723220SNishanth Menon * @dev_id: Device identifier this request is for 4269f723220SNishanth Menon * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 4279f723220SNishanth Menon * allowable programmed frequency and does not account for clock 4289f723220SNishanth Menon * tolerances and jitter. 4299f723220SNishanth Menon * @target_freq_hz: The target clock frequency. A frequency will be found 4309f723220SNishanth Menon * as close to this target frequency as possible. 4319f723220SNishanth Menon * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 4329f723220SNishanth Menon * allowable programmed frequency and does not account for clock 4339f723220SNishanth Menon * tolerances and jitter. 43481f4458cSTero Kristo * @clk_id: Clock identifier for the device for this request. Set to 43581f4458cSTero Kristo * 255 if clock identifier is greater than or equal to 255. 43681f4458cSTero Kristo * @clk_id_32: Clock identifier if @clk_id is set to 255. 4379f723220SNishanth Menon * 4389f723220SNishanth Menon * NOTE: Normally clock frequency management is automatically done by TISCI 4399f723220SNishanth Menon * entity. In case of specific requests, TISCI evaluates capability to achieve 4409f723220SNishanth Menon * requested frequency within provided range and responds with 4419f723220SNishanth Menon * result message. 4429f723220SNishanth Menon * 4439f723220SNishanth Menon * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 4449f723220SNishanth Menon * or NACK in case of inability to satisfy request. 4459f723220SNishanth Menon */ 4469f723220SNishanth Menon struct ti_sci_msg_req_query_clock_freq { 4479f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 4489f723220SNishanth Menon u32 dev_id; 4499f723220SNishanth Menon u64 min_freq_hz; 4509f723220SNishanth Menon u64 target_freq_hz; 4519f723220SNishanth Menon u64 max_freq_hz; 4529f723220SNishanth Menon u8 clk_id; 45381f4458cSTero Kristo u32 clk_id_32; 4549f723220SNishanth Menon } __packed; 4559f723220SNishanth Menon 4569f723220SNishanth Menon /** 4579f723220SNishanth Menon * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 4589f723220SNishanth Menon * @hdr: Generic Header 4599f723220SNishanth Menon * @freq_hz: Frequency that is the best match in Hz. 4609f723220SNishanth Menon * 4619f723220SNishanth Menon * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 4629f723220SNishanth Menon * cannot be satisfied, the message will be of type NACK. 4639f723220SNishanth Menon */ 4649f723220SNishanth Menon struct ti_sci_msg_resp_query_clock_freq { 4659f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 4669f723220SNishanth Menon u64 freq_hz; 4679f723220SNishanth Menon } __packed; 4689f723220SNishanth Menon 4699f723220SNishanth Menon /** 4709f723220SNishanth Menon * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 4719f723220SNishanth Menon * @hdr: Generic Header 4729f723220SNishanth Menon * @dev_id: Device identifier this request is for 4739f723220SNishanth Menon * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 4749f723220SNishanth Menon * allowable programmed frequency and does not account for clock 4759f723220SNishanth Menon * tolerances and jitter. 4769f723220SNishanth Menon * @target_freq_hz: The target clock frequency. The clock will be programmed 4779f723220SNishanth Menon * at a rate as close to this target frequency as possible. 4789f723220SNishanth Menon * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 4799f723220SNishanth Menon * allowable programmed frequency and does not account for clock 4809f723220SNishanth Menon * tolerances and jitter. 48181f4458cSTero Kristo * @clk_id: Clock identifier for the device for this request. Set to 48281f4458cSTero Kristo * 255 if clock ID is greater than or equal to 255. 48381f4458cSTero Kristo * @clk_id_32: Clock identifier if @clk_id field is set to 255. 4849f723220SNishanth Menon * 4859f723220SNishanth Menon * NOTE: Normally clock frequency management is automatically done by TISCI 4869f723220SNishanth Menon * entity. In case of specific requests, TISCI evaluates capability to achieve 4879f723220SNishanth Menon * requested range and responds with success/failure message. 4889f723220SNishanth Menon * 4899f723220SNishanth Menon * This sets the desired frequency for a clock within an allowable 4909f723220SNishanth Menon * range. This message will fail on an enabled clock unless 4919f723220SNishanth Menon * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 4929f723220SNishanth Menon * if other clocks have their frequency modified due to this message, 4939f723220SNishanth Menon * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 4949f723220SNishanth Menon * 4959f723220SNishanth Menon * Calling set frequency on a clock input to the SoC pseudo-device will 4969f723220SNishanth Menon * inform the PMMC of that clock's frequency. Setting a frequency of 4979f723220SNishanth Menon * zero will indicate the clock is disabled. 4989f723220SNishanth Menon * 4999f723220SNishanth Menon * Calling set frequency on clock outputs from the SoC pseudo-device will 5009f723220SNishanth Menon * function similarly to setting the clock frequency on a device. 5019f723220SNishanth Menon * 5029f723220SNishanth Menon * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 5039f723220SNishanth Menon * message. 5049f723220SNishanth Menon */ 5059f723220SNishanth Menon struct ti_sci_msg_req_set_clock_freq { 5069f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 5079f723220SNishanth Menon u32 dev_id; 5089f723220SNishanth Menon u64 min_freq_hz; 5099f723220SNishanth Menon u64 target_freq_hz; 5109f723220SNishanth Menon u64 max_freq_hz; 5119f723220SNishanth Menon u8 clk_id; 51281f4458cSTero Kristo u32 clk_id_32; 5139f723220SNishanth Menon } __packed; 5149f723220SNishanth Menon 5159f723220SNishanth Menon /** 5169f723220SNishanth Menon * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 5179f723220SNishanth Menon * @hdr: Generic Header 5189f723220SNishanth Menon * @dev_id: Device identifier this request is for 51981f4458cSTero Kristo * @clk_id: Clock identifier for the device for this request. Set to 52081f4458cSTero Kristo * 255 if clock ID is greater than or equal to 255. 52181f4458cSTero Kristo * @clk_id_32: Clock identifier if @clk_id field is set to 255. 5229f723220SNishanth Menon * 5239f723220SNishanth Menon * NOTE: Normally clock frequency management is automatically done by TISCI 5249f723220SNishanth Menon * entity. In some cases, clock frequencies are configured by host. 5259f723220SNishanth Menon * 5269f723220SNishanth Menon * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 5279f723220SNishanth Menon * that the clock is currently at. 5289f723220SNishanth Menon */ 5299f723220SNishanth Menon struct ti_sci_msg_req_get_clock_freq { 5309f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 5319f723220SNishanth Menon u32 dev_id; 5329f723220SNishanth Menon u8 clk_id; 53381f4458cSTero Kristo u32 clk_id_32; 5349f723220SNishanth Menon } __packed; 5359f723220SNishanth Menon 5369f723220SNishanth Menon /** 5379f723220SNishanth Menon * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 5389f723220SNishanth Menon * @hdr: Generic Header 5399f723220SNishanth Menon * @freq_hz: Frequency that the clock is currently on, in Hz. 5409f723220SNishanth Menon * 5419f723220SNishanth Menon * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 5429f723220SNishanth Menon */ 5439f723220SNishanth Menon struct ti_sci_msg_resp_get_clock_freq { 5449f723220SNishanth Menon struct ti_sci_msg_hdr hdr; 5459f723220SNishanth Menon u64 freq_hz; 5469f723220SNishanth Menon } __packed; 5479f723220SNishanth Menon 5489c19fb68SLokesh Vutla #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 5499c19fb68SLokesh Vutla 5509c19fb68SLokesh Vutla /** 5519c19fb68SLokesh Vutla * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 5529c19fb68SLokesh Vutla * range of resources. 5539c19fb68SLokesh Vutla * @hdr: Generic Header 5549c19fb68SLokesh Vutla * @type: Unique resource assignment type 5559c19fb68SLokesh Vutla * @subtype: Resource assignment subtype within the resource type. 5569c19fb68SLokesh Vutla * @secondary_host: Host processing entity to which the resources are 5579c19fb68SLokesh Vutla * allocated. This is required only when the destination 5589c19fb68SLokesh Vutla * host id id different from ti sci interface host id, 5599c19fb68SLokesh Vutla * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 5609c19fb68SLokesh Vutla * 5619c19fb68SLokesh Vutla * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 5629c19fb68SLokesh Vutla * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 5639c19fb68SLokesh Vutla */ 5649c19fb68SLokesh Vutla struct ti_sci_msg_req_get_resource_range { 5659c19fb68SLokesh Vutla struct ti_sci_msg_hdr hdr; 5669c19fb68SLokesh Vutla #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 5679c19fb68SLokesh Vutla #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 5689c19fb68SLokesh Vutla u16 type; 5699c19fb68SLokesh Vutla u8 subtype; 5709c19fb68SLokesh Vutla u8 secondary_host; 5719c19fb68SLokesh Vutla } __packed; 5729c19fb68SLokesh Vutla 5739c19fb68SLokesh Vutla /** 5749c19fb68SLokesh Vutla * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 5759c19fb68SLokesh Vutla * @hdr: Generic Header 576519c5c0cSPeter Ujfalusi * @range_start: Start index of the first resource range. 577519c5c0cSPeter Ujfalusi * @range_num: Number of resources in the first range. 578519c5c0cSPeter Ujfalusi * @range_start_sec: Start index of the second resource range. 579519c5c0cSPeter Ujfalusi * @range_num_sec: Number of resources in the second range. 5809c19fb68SLokesh Vutla * 5819c19fb68SLokesh Vutla * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 5829c19fb68SLokesh Vutla */ 5839c19fb68SLokesh Vutla struct ti_sci_msg_resp_get_resource_range { 5849c19fb68SLokesh Vutla struct ti_sci_msg_hdr hdr; 5859c19fb68SLokesh Vutla u16 range_start; 5869c19fb68SLokesh Vutla u16 range_num; 587519c5c0cSPeter Ujfalusi u16 range_start_sec; 588519c5c0cSPeter Ujfalusi u16 range_num_sec; 5899c19fb68SLokesh Vutla } __packed; 5909c19fb68SLokesh Vutla 591997b001fSLokesh Vutla /** 592997b001fSLokesh Vutla * struct ti_sci_msg_req_manage_irq - Request to configure/release the route 593997b001fSLokesh Vutla * between the dev and the host. 594997b001fSLokesh Vutla * @hdr: Generic Header 595997b001fSLokesh Vutla * @valid_params: Bit fields defining the validity of interrupt source 596997b001fSLokesh Vutla * parameters. If a bit is not set, then corresponding 597997b001fSLokesh Vutla * field is not valid and will not be used for route set. 598997b001fSLokesh Vutla * Bit field definitions: 599997b001fSLokesh Vutla * 0 - Valid bit for @dst_id 600997b001fSLokesh Vutla * 1 - Valid bit for @dst_host_irq 601997b001fSLokesh Vutla * 2 - Valid bit for @ia_id 602997b001fSLokesh Vutla * 3 - Valid bit for @vint 603997b001fSLokesh Vutla * 4 - Valid bit for @global_event 604997b001fSLokesh Vutla * 5 - Valid bit for @vint_status_bit_index 605997b001fSLokesh Vutla * 31 - Valid bit for @secondary_host 606997b001fSLokesh Vutla * @src_id: IRQ source peripheral ID. 607997b001fSLokesh Vutla * @src_index: IRQ source index within the peripheral 608997b001fSLokesh Vutla * @dst_id: IRQ Destination ID. Based on the architecture it can be 609997b001fSLokesh Vutla * IRQ controller or host processor ID. 610997b001fSLokesh Vutla * @dst_host_irq: IRQ number of the destination host IRQ controller 611997b001fSLokesh Vutla * @ia_id: Device ID of the interrupt aggregator in which the 612997b001fSLokesh Vutla * vint resides. 613997b001fSLokesh Vutla * @vint: Virtual interrupt number if the interrupt route 614997b001fSLokesh Vutla * is through an interrupt aggregator. 615997b001fSLokesh Vutla * @global_event: Global event that is to be mapped to interrupt 616997b001fSLokesh Vutla * aggregator virtual interrupt status bit. 617997b001fSLokesh Vutla * @vint_status_bit: Virtual interrupt status bit if the interrupt route 618997b001fSLokesh Vutla * utilizes an interrupt aggregator status bit. 619997b001fSLokesh Vutla * @secondary_host: Host ID of the IRQ destination computing entity. This is 620997b001fSLokesh Vutla * required only when destination host id is different 621997b001fSLokesh Vutla * from ti sci interface host id. 622997b001fSLokesh Vutla * 623997b001fSLokesh Vutla * Request type is TI_SCI_MSG_SET/RELEASE_IRQ. 624997b001fSLokesh Vutla * Response is generic ACK / NACK message. 625997b001fSLokesh Vutla */ 626997b001fSLokesh Vutla struct ti_sci_msg_req_manage_irq { 627997b001fSLokesh Vutla struct ti_sci_msg_hdr hdr; 628997b001fSLokesh Vutla #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0) 629997b001fSLokesh Vutla #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1) 630997b001fSLokesh Vutla #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2) 631997b001fSLokesh Vutla #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3) 632997b001fSLokesh Vutla #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4) 633997b001fSLokesh Vutla #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5) 634997b001fSLokesh Vutla #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31) 635997b001fSLokesh Vutla u32 valid_params; 636997b001fSLokesh Vutla u16 src_id; 637997b001fSLokesh Vutla u16 src_index; 638997b001fSLokesh Vutla u16 dst_id; 639997b001fSLokesh Vutla u16 dst_host_irq; 640997b001fSLokesh Vutla u16 ia_id; 641997b001fSLokesh Vutla u16 vint; 642997b001fSLokesh Vutla u16 global_event; 643997b001fSLokesh Vutla u8 vint_status_bit; 644997b001fSLokesh Vutla u8 secondary_host; 645997b001fSLokesh Vutla } __packed; 646997b001fSLokesh Vutla 64768608b5eSPeter Ujfalusi /** 64868608b5eSPeter Ujfalusi * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 64968608b5eSPeter Ujfalusi * 65068608b5eSPeter Ujfalusi * Configures the non-real-time registers of a Navigator Subsystem ring. 65168608b5eSPeter Ujfalusi * @hdr: Generic Header 65268608b5eSPeter Ujfalusi * @valid_params: Bitfield defining validity of ring configuration parameters. 65368608b5eSPeter Ujfalusi * The ring configuration fields are not valid, and will not be used for 65468608b5eSPeter Ujfalusi * ring configuration, if their corresponding valid bit is zero. 65568608b5eSPeter Ujfalusi * Valid bit usage: 65668608b5eSPeter Ujfalusi * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 65768608b5eSPeter Ujfalusi * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 65868608b5eSPeter Ujfalusi * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 65968608b5eSPeter Ujfalusi * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 66068608b5eSPeter Ujfalusi * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 66168608b5eSPeter Ujfalusi * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 662*3c201753SPeter Ujfalusi * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid 663*3c201753SPeter Ujfalusi * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL 66468608b5eSPeter Ujfalusi * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 66568608b5eSPeter Ujfalusi * @index: ring index to be configured. 66668608b5eSPeter Ujfalusi * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 66768608b5eSPeter Ujfalusi * RING_BA_LO register 66868608b5eSPeter Ujfalusi * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 66968608b5eSPeter Ujfalusi * RING_BA_HI register. 67068608b5eSPeter Ujfalusi * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 67168608b5eSPeter Ujfalusi * modes. 67268608b5eSPeter Ujfalusi * @mode: Specifies the mode the ring is to be configured. 67368608b5eSPeter Ujfalusi * @size: Specifies encoded ring element size. To calculate the encoded size use 67468608b5eSPeter Ujfalusi * the formula (log2(size_bytes) - 2), where size_bytes cannot be 67568608b5eSPeter Ujfalusi * greater than 256. 67668608b5eSPeter Ujfalusi * @order_id: Specifies the ring's bus order ID. 677*3c201753SPeter Ujfalusi * @virtid: Ring virt ID value 678*3c201753SPeter Ujfalusi * @asel: Ring ASEL (address select) value to be set into the ASEL field of the 679*3c201753SPeter Ujfalusi * ring's RING_BA_HI register. 68068608b5eSPeter Ujfalusi */ 68168608b5eSPeter Ujfalusi struct ti_sci_msg_rm_ring_cfg_req { 68268608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 68368608b5eSPeter Ujfalusi u32 valid_params; 68468608b5eSPeter Ujfalusi u16 nav_id; 68568608b5eSPeter Ujfalusi u16 index; 68668608b5eSPeter Ujfalusi u32 addr_lo; 68768608b5eSPeter Ujfalusi u32 addr_hi; 68868608b5eSPeter Ujfalusi u32 count; 68968608b5eSPeter Ujfalusi u8 mode; 69068608b5eSPeter Ujfalusi u8 size; 69168608b5eSPeter Ujfalusi u8 order_id; 692*3c201753SPeter Ujfalusi u16 virtid; 693*3c201753SPeter Ujfalusi u8 asel; 69468608b5eSPeter Ujfalusi } __packed; 69568608b5eSPeter Ujfalusi 69668608b5eSPeter Ujfalusi /** 69768608b5eSPeter Ujfalusi * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 69868608b5eSPeter Ujfalusi * thread 69968608b5eSPeter Ujfalusi * @hdr: Generic Header 70068608b5eSPeter Ujfalusi * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 70168608b5eSPeter Ujfalusi * used to pair the source and destination threads. 70268608b5eSPeter Ujfalusi * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 70368608b5eSPeter Ujfalusi * 70468608b5eSPeter Ujfalusi * UDMAP transmit channels mapped to source threads will have their 70568608b5eSPeter Ujfalusi * TCHAN_THRD_ID register programmed with the destination thread if the pairing 70668608b5eSPeter Ujfalusi * is successful. 70768608b5eSPeter Ujfalusi 70868608b5eSPeter Ujfalusi * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 70968608b5eSPeter Ujfalusi * PSI-L destination threads start at index 0x8000. The request is NACK'd if 71068608b5eSPeter Ujfalusi * the destination thread is not greater than or equal to 0x8000. 71168608b5eSPeter Ujfalusi * 71268608b5eSPeter Ujfalusi * UDMAP receive channels mapped to destination threads will have their 71368608b5eSPeter Ujfalusi * RCHAN_THRD_ID register programmed with the source thread if the pairing 71468608b5eSPeter Ujfalusi * is successful. 71568608b5eSPeter Ujfalusi * 71668608b5eSPeter Ujfalusi * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 71768608b5eSPeter Ujfalusi * message. 71868608b5eSPeter Ujfalusi */ 71968608b5eSPeter Ujfalusi struct ti_sci_msg_psil_pair { 72068608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 72168608b5eSPeter Ujfalusi u32 nav_id; 72268608b5eSPeter Ujfalusi u32 src_thread; 72368608b5eSPeter Ujfalusi u32 dst_thread; 72468608b5eSPeter Ujfalusi } __packed; 72568608b5eSPeter Ujfalusi 72668608b5eSPeter Ujfalusi /** 72768608b5eSPeter Ujfalusi * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 72868608b5eSPeter Ujfalusi * destination thread 72968608b5eSPeter Ujfalusi * @hdr: Generic Header 73068608b5eSPeter Ujfalusi * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 73168608b5eSPeter Ujfalusi * used to unpair the source and destination threads. 73268608b5eSPeter Ujfalusi * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 73368608b5eSPeter Ujfalusi * 73468608b5eSPeter Ujfalusi * UDMAP transmit channels mapped to source threads will have their 73568608b5eSPeter Ujfalusi * TCHAN_THRD_ID register cleared if the unpairing is successful. 73668608b5eSPeter Ujfalusi * 73768608b5eSPeter Ujfalusi * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 73868608b5eSPeter Ujfalusi * PSI-L destination threads start at index 0x8000. The request is NACK'd if 73968608b5eSPeter Ujfalusi * the destination thread is not greater than or equal to 0x8000. 74068608b5eSPeter Ujfalusi * 74168608b5eSPeter Ujfalusi * UDMAP receive channels mapped to destination threads will have their 74268608b5eSPeter Ujfalusi * RCHAN_THRD_ID register cleared if the unpairing is successful. 74368608b5eSPeter Ujfalusi * 74468608b5eSPeter Ujfalusi * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 74568608b5eSPeter Ujfalusi * message. 74668608b5eSPeter Ujfalusi */ 74768608b5eSPeter Ujfalusi struct ti_sci_msg_psil_unpair { 74868608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 74968608b5eSPeter Ujfalusi u32 nav_id; 75068608b5eSPeter Ujfalusi u32 src_thread; 75168608b5eSPeter Ujfalusi u32 dst_thread; 75268608b5eSPeter Ujfalusi } __packed; 75368608b5eSPeter Ujfalusi 75468608b5eSPeter Ujfalusi /** 75568608b5eSPeter Ujfalusi * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration 75668608b5eSPeter Ujfalusi * message 75768608b5eSPeter Ujfalusi * @hdr: Generic Header 75868608b5eSPeter Ujfalusi * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 75968608b5eSPeter Ujfalusi * allocated 76068608b5eSPeter Ujfalusi * @flow_index: UDMAP receive flow index for non-optional configuration. 76168608b5eSPeter Ujfalusi * @rx_ch_index: Specifies the index of the receive channel using the flow_index 76268608b5eSPeter Ujfalusi * @rx_einfo_present: UDMAP receive flow extended packet info present. 76368608b5eSPeter Ujfalusi * @rx_psinfo_present: UDMAP receive flow PS words present. 76468608b5eSPeter Ujfalusi * @rx_error_handling: UDMAP receive flow error handling configuration. Valid 76568608b5eSPeter Ujfalusi * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY. 76668608b5eSPeter Ujfalusi * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of 76768608b5eSPeter Ujfalusi * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO. 76868608b5eSPeter Ujfalusi * @rx_sop_offset: UDMAP receive flow start of packet offset. 76968608b5eSPeter Ujfalusi * @rx_dest_qnum: UDMAP receive flow destination queue number. 77068608b5eSPeter Ujfalusi * @rx_ps_location: UDMAP receive flow PS words location. 77168608b5eSPeter Ujfalusi * 0 - end of packet descriptor 77268608b5eSPeter Ujfalusi * 1 - Beginning of the data buffer 77368608b5eSPeter Ujfalusi * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant 77468608b5eSPeter Ujfalusi * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant 77568608b5eSPeter Ujfalusi * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant 77668608b5eSPeter Ujfalusi * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant 77768608b5eSPeter Ujfalusi * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector 77868608b5eSPeter Ujfalusi * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector 77968608b5eSPeter Ujfalusi * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector 78068608b5eSPeter Ujfalusi * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector 78168608b5eSPeter Ujfalusi * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue 78268608b5eSPeter Ujfalusi * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be 78368608b5eSPeter Ujfalusi * configured and sent. 78468608b5eSPeter Ujfalusi * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0. 78568608b5eSPeter Ujfalusi * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1. 78668608b5eSPeter Ujfalusi * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2. 78768608b5eSPeter Ujfalusi * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3. 78868608b5eSPeter Ujfalusi * 78968608b5eSPeter Ujfalusi * For detailed information on the settings, see the UDMAP section of the TRM. 79068608b5eSPeter Ujfalusi */ 79168608b5eSPeter Ujfalusi struct ti_sci_msg_udmap_rx_flow_cfg { 79268608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 79368608b5eSPeter Ujfalusi u32 nav_id; 79468608b5eSPeter Ujfalusi u32 flow_index; 79568608b5eSPeter Ujfalusi u32 rx_ch_index; 79668608b5eSPeter Ujfalusi u8 rx_einfo_present; 79768608b5eSPeter Ujfalusi u8 rx_psinfo_present; 79868608b5eSPeter Ujfalusi u8 rx_error_handling; 79968608b5eSPeter Ujfalusi u8 rx_desc_type; 80068608b5eSPeter Ujfalusi u16 rx_sop_offset; 80168608b5eSPeter Ujfalusi u16 rx_dest_qnum; 80268608b5eSPeter Ujfalusi u8 rx_ps_location; 80368608b5eSPeter Ujfalusi u8 rx_src_tag_hi; 80468608b5eSPeter Ujfalusi u8 rx_src_tag_lo; 80568608b5eSPeter Ujfalusi u8 rx_dest_tag_hi; 80668608b5eSPeter Ujfalusi u8 rx_dest_tag_lo; 80768608b5eSPeter Ujfalusi u8 rx_src_tag_hi_sel; 80868608b5eSPeter Ujfalusi u8 rx_src_tag_lo_sel; 80968608b5eSPeter Ujfalusi u8 rx_dest_tag_hi_sel; 81068608b5eSPeter Ujfalusi u8 rx_dest_tag_lo_sel; 81168608b5eSPeter Ujfalusi u8 rx_size_thresh_en; 81268608b5eSPeter Ujfalusi u16 rx_fdq0_sz0_qnum; 81368608b5eSPeter Ujfalusi u16 rx_fdq1_qnum; 81468608b5eSPeter Ujfalusi u16 rx_fdq2_qnum; 81568608b5eSPeter Ujfalusi u16 rx_fdq3_qnum; 81668608b5eSPeter Ujfalusi } __packed; 81768608b5eSPeter Ujfalusi 81868608b5eSPeter Ujfalusi /** 81968608b5eSPeter Ujfalusi * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive 82068608b5eSPeter Ujfalusi * flow optional configuration 82168608b5eSPeter Ujfalusi * @hdr: Generic Header 82268608b5eSPeter Ujfalusi * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 82368608b5eSPeter Ujfalusi * allocated 82468608b5eSPeter Ujfalusi * @flow_index: UDMAP receive flow index for optional configuration. 82568608b5eSPeter Ujfalusi * @rx_ch_index: Specifies the index of the receive channel using the flow_index 82668608b5eSPeter Ujfalusi * @rx_size_thresh0: UDMAP receive flow packet size threshold 0. 82768608b5eSPeter Ujfalusi * @rx_size_thresh1: UDMAP receive flow packet size threshold 1. 82868608b5eSPeter Ujfalusi * @rx_size_thresh2: UDMAP receive flow packet size threshold 2. 82968608b5eSPeter Ujfalusi * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size 83068608b5eSPeter Ujfalusi * threshold 1. 83168608b5eSPeter Ujfalusi * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size 83268608b5eSPeter Ujfalusi * threshold 2. 83368608b5eSPeter Ujfalusi * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size 83468608b5eSPeter Ujfalusi * threshold 3. 83568608b5eSPeter Ujfalusi * 83668608b5eSPeter Ujfalusi * For detailed information on the settings, see the UDMAP section of the TRM. 83768608b5eSPeter Ujfalusi */ 83868608b5eSPeter Ujfalusi struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { 83968608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 84068608b5eSPeter Ujfalusi u32 nav_id; 84168608b5eSPeter Ujfalusi u32 flow_index; 84268608b5eSPeter Ujfalusi u32 rx_ch_index; 84368608b5eSPeter Ujfalusi u16 rx_size_thresh0; 84468608b5eSPeter Ujfalusi u16 rx_size_thresh1; 84568608b5eSPeter Ujfalusi u16 rx_size_thresh2; 84668608b5eSPeter Ujfalusi u16 rx_fdq0_sz1_qnum; 84768608b5eSPeter Ujfalusi u16 rx_fdq0_sz2_qnum; 84868608b5eSPeter Ujfalusi u16 rx_fdq0_sz3_qnum; 84968608b5eSPeter Ujfalusi } __packed; 85068608b5eSPeter Ujfalusi 85168608b5eSPeter Ujfalusi /** 85268608b5eSPeter Ujfalusi * Configures a Navigator Subsystem UDMAP transmit channel 85368608b5eSPeter Ujfalusi * 85468608b5eSPeter Ujfalusi * Configures the non-real-time registers of a Navigator Subsystem UDMAP 85568608b5eSPeter Ujfalusi * transmit channel. The channel index must be assigned to the host defined 85668608b5eSPeter Ujfalusi * in the TISCI header via the RM board configuration resource assignment 85768608b5eSPeter Ujfalusi * range list. 85868608b5eSPeter Ujfalusi * 85968608b5eSPeter Ujfalusi * @hdr: Generic Header 86068608b5eSPeter Ujfalusi * 86168608b5eSPeter Ujfalusi * @valid_params: Bitfield defining validity of tx channel configuration 86268608b5eSPeter Ujfalusi * parameters. The tx channel configuration fields are not valid, and will not 86368608b5eSPeter Ujfalusi * be used for ch configuration, if their corresponding valid bit is zero. 86468608b5eSPeter Ujfalusi * Valid bit usage: 86568608b5eSPeter Ujfalusi * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 86668608b5eSPeter Ujfalusi * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 86768608b5eSPeter Ujfalusi * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 86868608b5eSPeter Ujfalusi * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 86968608b5eSPeter Ujfalusi * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 87068608b5eSPeter Ujfalusi * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 87168608b5eSPeter Ujfalusi * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 87268608b5eSPeter Ujfalusi * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 87368608b5eSPeter Ujfalusi * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 87468608b5eSPeter Ujfalusi * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 87568608b5eSPeter Ujfalusi * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 87668608b5eSPeter Ujfalusi * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 87768608b5eSPeter Ujfalusi * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 87868608b5eSPeter Ujfalusi * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 87968608b5eSPeter Ujfalusi * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size 8801c552e08SPeter Ujfalusi * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype 881ce1feed5SPeter Ujfalusi * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type 88268608b5eSPeter Ujfalusi * 88368608b5eSPeter Ujfalusi * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 88468608b5eSPeter Ujfalusi * 88568608b5eSPeter Ujfalusi * @index: UDMAP transmit channel index. 88668608b5eSPeter Ujfalusi * 88768608b5eSPeter Ujfalusi * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 88868608b5eSPeter Ujfalusi * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 88968608b5eSPeter Ujfalusi * register. 89068608b5eSPeter Ujfalusi * 89168608b5eSPeter Ujfalusi * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 89268608b5eSPeter Ujfalusi * configuration to be programmed into the tx_filt_einfo field of the 89368608b5eSPeter Ujfalusi * channel's TCHAN_TCFG register. 89468608b5eSPeter Ujfalusi * 89568608b5eSPeter Ujfalusi * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 89668608b5eSPeter Ujfalusi * configuration to be programmed into the tx_filt_pswords field of the 89768608b5eSPeter Ujfalusi * channel's TCHAN_TCFG register. 89868608b5eSPeter Ujfalusi * 89968608b5eSPeter Ujfalusi * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 90068608b5eSPeter Ujfalusi * interpretation configuration to be programmed into the tx_atype field of 90168608b5eSPeter Ujfalusi * the channel's TCHAN_TCFG register. 90268608b5eSPeter Ujfalusi * 90368608b5eSPeter Ujfalusi * @tx_chan_type: UDMAP transmit channel functional channel type and work 90468608b5eSPeter Ujfalusi * passing mechanism configuration to be programmed into the tx_chan_type 90568608b5eSPeter Ujfalusi * field of the channel's TCHAN_TCFG register. 90668608b5eSPeter Ujfalusi * 90768608b5eSPeter Ujfalusi * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 90868608b5eSPeter Ujfalusi * configuration to be programmed into the tx_supr_tdpkt field of the channel's 90968608b5eSPeter Ujfalusi * TCHAN_TCFG register. 91068608b5eSPeter Ujfalusi * 91168608b5eSPeter Ujfalusi * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 91268608b5eSPeter Ujfalusi * fetch configuration to be programmed into the tx_fetch_size field of the 91368608b5eSPeter Ujfalusi * channel's TCHAN_TCFG register. The user must make sure to set the maximum 91468608b5eSPeter Ujfalusi * word count that can pass through the channel for any allowed descriptor type. 91568608b5eSPeter Ujfalusi * 91668608b5eSPeter Ujfalusi * @tx_credit_count: UDMAP transmit channel transfer request credit count 91768608b5eSPeter Ujfalusi * configuration to be programmed into the count field of the TCHAN_TCREDIT 91868608b5eSPeter Ujfalusi * register. Specifies how many credits for complete TRs are available. 91968608b5eSPeter Ujfalusi * 92068608b5eSPeter Ujfalusi * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 92168608b5eSPeter Ujfalusi * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 92268608b5eSPeter Ujfalusi * completion queue must be assigned to the host, or a subordinate of the host, 92368608b5eSPeter Ujfalusi * requesting configuration of the transmit channel. 92468608b5eSPeter Ujfalusi * 92568608b5eSPeter Ujfalusi * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 92668608b5eSPeter Ujfalusi * into the priority field of the channel's TCHAN_TPRI_CTRL register. 92768608b5eSPeter Ujfalusi * 92868608b5eSPeter Ujfalusi * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 92968608b5eSPeter Ujfalusi * qos field of the channel's TCHAN_TPRI_CTRL register. 93068608b5eSPeter Ujfalusi * 93168608b5eSPeter Ujfalusi * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 93268608b5eSPeter Ujfalusi * the orderid field of the channel's TCHAN_TPRI_CTRL register. 93368608b5eSPeter Ujfalusi * 93468608b5eSPeter Ujfalusi * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 93568608b5eSPeter Ujfalusi * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 93668608b5eSPeter Ujfalusi * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 93768608b5eSPeter Ujfalusi * section of the TRM for restrictions regarding this parameter. 93868608b5eSPeter Ujfalusi * 93968608b5eSPeter Ujfalusi * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 94068608b5eSPeter Ujfalusi * configuration to be programmed into the priority field of the channel's 94168608b5eSPeter Ujfalusi * TCHAN_TST_SCHED register. 94268608b5eSPeter Ujfalusi * 94368608b5eSPeter Ujfalusi * @tx_burst_size: UDMAP transmit channel burst size configuration to be 94468608b5eSPeter Ujfalusi * programmed into the tx_burst_size field of the TCHAN_TCFG register. 9451c552e08SPeter Ujfalusi * 9461c552e08SPeter Ujfalusi * @tx_tdtype: UDMAP transmit channel teardown type configuration to be 9471c552e08SPeter Ujfalusi * programmed into the tdtype field of the TCHAN_TCFG register: 9481c552e08SPeter Ujfalusi * 0 - Return immediately 9491c552e08SPeter Ujfalusi * 1 - Wait for completion message from remote peer 950ce1feed5SPeter Ujfalusi * 951ce1feed5SPeter Ujfalusi * @extended_ch_type: Valid for BCDMA. 952ce1feed5SPeter Ujfalusi * 0 - the channel is split tx channel (tchan) 953ce1feed5SPeter Ujfalusi * 1 - the channel is block copy channel (bchan) 95468608b5eSPeter Ujfalusi */ 95568608b5eSPeter Ujfalusi struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 95668608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 95768608b5eSPeter Ujfalusi u32 valid_params; 95868608b5eSPeter Ujfalusi u16 nav_id; 95968608b5eSPeter Ujfalusi u16 index; 96068608b5eSPeter Ujfalusi u8 tx_pause_on_err; 96168608b5eSPeter Ujfalusi u8 tx_filt_einfo; 96268608b5eSPeter Ujfalusi u8 tx_filt_pswords; 96368608b5eSPeter Ujfalusi u8 tx_atype; 96468608b5eSPeter Ujfalusi u8 tx_chan_type; 96568608b5eSPeter Ujfalusi u8 tx_supr_tdpkt; 96668608b5eSPeter Ujfalusi u16 tx_fetch_size; 96768608b5eSPeter Ujfalusi u8 tx_credit_count; 96868608b5eSPeter Ujfalusi u16 txcq_qnum; 96968608b5eSPeter Ujfalusi u8 tx_priority; 97068608b5eSPeter Ujfalusi u8 tx_qos; 97168608b5eSPeter Ujfalusi u8 tx_orderid; 97268608b5eSPeter Ujfalusi u16 fdepth; 97368608b5eSPeter Ujfalusi u8 tx_sched_priority; 97468608b5eSPeter Ujfalusi u8 tx_burst_size; 9751c552e08SPeter Ujfalusi u8 tx_tdtype; 976ce1feed5SPeter Ujfalusi u8 extended_ch_type; 97768608b5eSPeter Ujfalusi } __packed; 97868608b5eSPeter Ujfalusi 97968608b5eSPeter Ujfalusi /** 98068608b5eSPeter Ujfalusi * Configures a Navigator Subsystem UDMAP receive channel 98168608b5eSPeter Ujfalusi * 98268608b5eSPeter Ujfalusi * Configures the non-real-time registers of a Navigator Subsystem UDMAP 98368608b5eSPeter Ujfalusi * receive channel. The channel index must be assigned to the host defined 98468608b5eSPeter Ujfalusi * in the TISCI header via the RM board configuration resource assignment 98568608b5eSPeter Ujfalusi * range list. 98668608b5eSPeter Ujfalusi * 98768608b5eSPeter Ujfalusi * @hdr: Generic Header 98868608b5eSPeter Ujfalusi * 98968608b5eSPeter Ujfalusi * @valid_params: Bitfield defining validity of rx channel configuration 99068608b5eSPeter Ujfalusi * parameters. 99168608b5eSPeter Ujfalusi * The rx channel configuration fields are not valid, and will not be used for 99268608b5eSPeter Ujfalusi * ch configuration, if their corresponding valid bit is zero. 99368608b5eSPeter Ujfalusi * Valid bit usage: 99468608b5eSPeter Ujfalusi * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 99568608b5eSPeter Ujfalusi * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 99668608b5eSPeter Ujfalusi * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 99768608b5eSPeter Ujfalusi * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 99868608b5eSPeter Ujfalusi * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 99968608b5eSPeter Ujfalusi * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 100068608b5eSPeter Ujfalusi * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 100168608b5eSPeter Ujfalusi * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 100268608b5eSPeter Ujfalusi * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 100368608b5eSPeter Ujfalusi * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 100468608b5eSPeter Ujfalusi * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 100568608b5eSPeter Ujfalusi * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 100668608b5eSPeter Ujfalusi * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 100768608b5eSPeter Ujfalusi * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size 100868608b5eSPeter Ujfalusi * 100968608b5eSPeter Ujfalusi * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 101068608b5eSPeter Ujfalusi * 101168608b5eSPeter Ujfalusi * @index: UDMAP receive channel index. 101268608b5eSPeter Ujfalusi * 101368608b5eSPeter Ujfalusi * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 101468608b5eSPeter Ujfalusi * fetch configuration to be programmed into the rx_fetch_size field of the 101568608b5eSPeter Ujfalusi * channel's RCHAN_RCFG register. 101668608b5eSPeter Ujfalusi * 101768608b5eSPeter Ujfalusi * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 101868608b5eSPeter Ujfalusi * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 101968608b5eSPeter Ujfalusi * The specified completion queue must be assigned to the host, or a subordinate 102068608b5eSPeter Ujfalusi * of the host, requesting configuration of the receive channel. 102168608b5eSPeter Ujfalusi * 102268608b5eSPeter Ujfalusi * @rx_priority: UDMAP receive channel receive priority value to be programmed 102368608b5eSPeter Ujfalusi * into the priority field of the channel's RCHAN_RPRI_CTRL register. 102468608b5eSPeter Ujfalusi * 102568608b5eSPeter Ujfalusi * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 102668608b5eSPeter Ujfalusi * qos field of the channel's RCHAN_RPRI_CTRL register. 102768608b5eSPeter Ujfalusi * 102868608b5eSPeter Ujfalusi * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 102968608b5eSPeter Ujfalusi * the orderid field of the channel's RCHAN_RPRI_CTRL register. 103068608b5eSPeter Ujfalusi * 103168608b5eSPeter Ujfalusi * @rx_sched_priority: UDMAP receive channel rx scheduling priority 103268608b5eSPeter Ujfalusi * configuration to be programmed into the priority field of the channel's 103368608b5eSPeter Ujfalusi * RCHAN_RST_SCHED register. 103468608b5eSPeter Ujfalusi * 103568608b5eSPeter Ujfalusi * @flowid_start: UDMAP receive channel additional flows starting index 103668608b5eSPeter Ujfalusi * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 103768608b5eSPeter Ujfalusi * register. Specifies the starting index for flow IDs the receive channel is to 103868608b5eSPeter Ujfalusi * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 103968608b5eSPeter Ujfalusi * set as valid and configured together. The starting flow ID set by 104068608b5eSPeter Ujfalusi * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 104168608b5eSPeter Ujfalusi * of flows beyond the default flows statically mapped to receive channels. 104268608b5eSPeter Ujfalusi * The additional flows must be assigned to the host, or a subordinate of the 104368608b5eSPeter Ujfalusi * host, requesting configuration of the receive channel. 104468608b5eSPeter Ujfalusi * 104568608b5eSPeter Ujfalusi * @flowid_cnt: UDMAP receive channel additional flows count configuration to 104668608b5eSPeter Ujfalusi * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 104768608b5eSPeter Ujfalusi * This field specifies how many flow IDs are in the additional contiguous range 104868608b5eSPeter Ujfalusi * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 104968608b5eSPeter Ujfalusi * set as valid and configured together. Disabling the valid_params field bit 105068608b5eSPeter Ujfalusi * for flowid_cnt indicates no flow IDs other than the default are to be 105168608b5eSPeter Ujfalusi * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 105268608b5eSPeter Ujfalusi * cannot be greater than the number of receive flows in the receive channel's 105368608b5eSPeter Ujfalusi * Navigator Subsystem. The additional flows must be assigned to the host, or a 105468608b5eSPeter Ujfalusi * subordinate of the host, requesting configuration of the receive channel. 105568608b5eSPeter Ujfalusi * 105668608b5eSPeter Ujfalusi * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 105768608b5eSPeter Ujfalusi * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 105868608b5eSPeter Ujfalusi * register. 105968608b5eSPeter Ujfalusi * 106068608b5eSPeter Ujfalusi * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 106168608b5eSPeter Ujfalusi * interpretation configuration to be programmed into the rx_atype field of the 106268608b5eSPeter Ujfalusi * channel's RCHAN_RCFG register. 106368608b5eSPeter Ujfalusi * 106468608b5eSPeter Ujfalusi * @rx_chan_type: UDMAP receive channel functional channel type and work passing 106568608b5eSPeter Ujfalusi * mechanism configuration to be programmed into the rx_chan_type field of the 106668608b5eSPeter Ujfalusi * channel's RCHAN_RCFG register. 106768608b5eSPeter Ujfalusi * 106868608b5eSPeter Ujfalusi * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 106968608b5eSPeter Ujfalusi * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 107068608b5eSPeter Ujfalusi * 107168608b5eSPeter Ujfalusi * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 107268608b5eSPeter Ujfalusi * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 107368608b5eSPeter Ujfalusi * 107468608b5eSPeter Ujfalusi * @rx_burst_size: UDMAP receive channel burst size configuration to be 107568608b5eSPeter Ujfalusi * programmed into the rx_burst_size field of the RCHAN_RCFG register. 107668608b5eSPeter Ujfalusi */ 107768608b5eSPeter Ujfalusi struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 107868608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 107968608b5eSPeter Ujfalusi u32 valid_params; 108068608b5eSPeter Ujfalusi u16 nav_id; 108168608b5eSPeter Ujfalusi u16 index; 108268608b5eSPeter Ujfalusi u16 rx_fetch_size; 108368608b5eSPeter Ujfalusi u16 rxcq_qnum; 108468608b5eSPeter Ujfalusi u8 rx_priority; 108568608b5eSPeter Ujfalusi u8 rx_qos; 108668608b5eSPeter Ujfalusi u8 rx_orderid; 108768608b5eSPeter Ujfalusi u8 rx_sched_priority; 108868608b5eSPeter Ujfalusi u16 flowid_start; 108968608b5eSPeter Ujfalusi u16 flowid_cnt; 109068608b5eSPeter Ujfalusi u8 rx_pause_on_err; 109168608b5eSPeter Ujfalusi u8 rx_atype; 109268608b5eSPeter Ujfalusi u8 rx_chan_type; 109368608b5eSPeter Ujfalusi u8 rx_ignore_short; 109468608b5eSPeter Ujfalusi u8 rx_ignore_long; 109568608b5eSPeter Ujfalusi u8 rx_burst_size; 109668608b5eSPeter Ujfalusi } __packed; 109768608b5eSPeter Ujfalusi 109868608b5eSPeter Ujfalusi /** 109968608b5eSPeter Ujfalusi * Configures a Navigator Subsystem UDMAP receive flow 110068608b5eSPeter Ujfalusi * 110168608b5eSPeter Ujfalusi * Configures a Navigator Subsystem UDMAP receive flow's registers. 110268608b5eSPeter Ujfalusi * Configuration does not include the flow registers which handle size-based 110368608b5eSPeter Ujfalusi * free descriptor queue routing. 110468608b5eSPeter Ujfalusi * 110568608b5eSPeter Ujfalusi * The flow index must be assigned to the host defined in the TISCI header via 110668608b5eSPeter Ujfalusi * the RM board configuration resource assignment range list. 110768608b5eSPeter Ujfalusi * 110868608b5eSPeter Ujfalusi * @hdr: Standard TISCI header 110968608b5eSPeter Ujfalusi * 111068608b5eSPeter Ujfalusi * @valid_params 111168608b5eSPeter Ujfalusi * Bitfield defining validity of rx flow configuration parameters. The 111268608b5eSPeter Ujfalusi * rx flow configuration fields are not valid, and will not be used for flow 111368608b5eSPeter Ujfalusi * configuration, if their corresponding valid bit is zero. Valid bit usage: 111468608b5eSPeter Ujfalusi * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 111568608b5eSPeter Ujfalusi * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 111668608b5eSPeter Ujfalusi * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 111768608b5eSPeter Ujfalusi * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 111868608b5eSPeter Ujfalusi * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 111968608b5eSPeter Ujfalusi * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 112068608b5eSPeter Ujfalusi * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 112168608b5eSPeter Ujfalusi * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 112268608b5eSPeter Ujfalusi * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 112368608b5eSPeter Ujfalusi * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 112468608b5eSPeter Ujfalusi * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 112568608b5eSPeter Ujfalusi * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 112668608b5eSPeter Ujfalusi * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 112768608b5eSPeter Ujfalusi * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 112868608b5eSPeter Ujfalusi * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 112968608b5eSPeter Ujfalusi * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 113068608b5eSPeter Ujfalusi * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 113168608b5eSPeter Ujfalusi * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 113268608b5eSPeter Ujfalusi * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 113368608b5eSPeter Ujfalusi * 113468608b5eSPeter Ujfalusi * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 113568608b5eSPeter Ujfalusi * allocated 113668608b5eSPeter Ujfalusi * 113768608b5eSPeter Ujfalusi * @flow_index: UDMAP receive flow index for non-optional configuration. 113868608b5eSPeter Ujfalusi * 113968608b5eSPeter Ujfalusi * @rx_einfo_present: 114068608b5eSPeter Ujfalusi * UDMAP receive flow extended packet info present configuration to be 114168608b5eSPeter Ujfalusi * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 114268608b5eSPeter Ujfalusi * 114368608b5eSPeter Ujfalusi * @rx_psinfo_present: 114468608b5eSPeter Ujfalusi * UDMAP receive flow PS words present configuration to be programmed into the 114568608b5eSPeter Ujfalusi * rx_psinfo_present field of the flow's RFLOW_RFA register. 114668608b5eSPeter Ujfalusi * 114768608b5eSPeter Ujfalusi * @rx_error_handling: 114868608b5eSPeter Ujfalusi * UDMAP receive flow error handling configuration to be programmed into the 114968608b5eSPeter Ujfalusi * rx_error_handling field of the flow's RFLOW_RFA register. 115068608b5eSPeter Ujfalusi * 115168608b5eSPeter Ujfalusi * @rx_desc_type: 115268608b5eSPeter Ujfalusi * UDMAP receive flow descriptor type configuration to be programmed into the 115368608b5eSPeter Ujfalusi * rx_desc_type field field of the flow's RFLOW_RFA register. 115468608b5eSPeter Ujfalusi * 115568608b5eSPeter Ujfalusi * @rx_sop_offset: 115668608b5eSPeter Ujfalusi * UDMAP receive flow start of packet offset configuration to be programmed 115768608b5eSPeter Ujfalusi * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 115868608b5eSPeter Ujfalusi * section of the TRM for more information on this setting. Valid values for 115968608b5eSPeter Ujfalusi * this field are 0-255 bytes. 116068608b5eSPeter Ujfalusi * 116168608b5eSPeter Ujfalusi * @rx_dest_qnum: 116268608b5eSPeter Ujfalusi * UDMAP receive flow destination queue configuration to be programmed into the 116368608b5eSPeter Ujfalusi * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 116468608b5eSPeter Ujfalusi * destination queue must be valid within the Navigator Subsystem and must be 116568608b5eSPeter Ujfalusi * owned by the host, or a subordinate of the host, requesting allocation and 116668608b5eSPeter Ujfalusi * configuration of the receive flow. 116768608b5eSPeter Ujfalusi * 116868608b5eSPeter Ujfalusi * @rx_src_tag_hi: 116968608b5eSPeter Ujfalusi * UDMAP receive flow source tag high byte constant configuration to be 117068608b5eSPeter Ujfalusi * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 117168608b5eSPeter Ujfalusi * See the UDMAP section of the TRM for more information on this setting. 117268608b5eSPeter Ujfalusi * 117368608b5eSPeter Ujfalusi * @rx_src_tag_lo: 117468608b5eSPeter Ujfalusi * UDMAP receive flow source tag low byte constant configuration to be 117568608b5eSPeter Ujfalusi * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 117668608b5eSPeter Ujfalusi * See the UDMAP section of the TRM for more information on this setting. 117768608b5eSPeter Ujfalusi * 117868608b5eSPeter Ujfalusi * @rx_dest_tag_hi: 117968608b5eSPeter Ujfalusi * UDMAP receive flow destination tag high byte constant configuration to be 118068608b5eSPeter Ujfalusi * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 118168608b5eSPeter Ujfalusi * See the UDMAP section of the TRM for more information on this setting. 118268608b5eSPeter Ujfalusi * 118368608b5eSPeter Ujfalusi * @rx_dest_tag_lo: 118468608b5eSPeter Ujfalusi * UDMAP receive flow destination tag low byte constant configuration to be 118568608b5eSPeter Ujfalusi * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 118668608b5eSPeter Ujfalusi * See the UDMAP section of the TRM for more information on this setting. 118768608b5eSPeter Ujfalusi * 118868608b5eSPeter Ujfalusi * @rx_src_tag_hi_sel: 118968608b5eSPeter Ujfalusi * UDMAP receive flow source tag high byte selector configuration to be 119068608b5eSPeter Ujfalusi * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 119168608b5eSPeter Ujfalusi * the UDMAP section of the TRM for more information on this setting. 119268608b5eSPeter Ujfalusi * 119368608b5eSPeter Ujfalusi * @rx_src_tag_lo_sel: 119468608b5eSPeter Ujfalusi * UDMAP receive flow source tag low byte selector configuration to be 119568608b5eSPeter Ujfalusi * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 119668608b5eSPeter Ujfalusi * the UDMAP section of the TRM for more information on this setting. 119768608b5eSPeter Ujfalusi * 119868608b5eSPeter Ujfalusi * @rx_dest_tag_hi_sel: 119968608b5eSPeter Ujfalusi * UDMAP receive flow destination tag high byte selector configuration to be 120068608b5eSPeter Ujfalusi * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 120168608b5eSPeter Ujfalusi * the UDMAP section of the TRM for more information on this setting. 120268608b5eSPeter Ujfalusi * 120368608b5eSPeter Ujfalusi * @rx_dest_tag_lo_sel: 120468608b5eSPeter Ujfalusi * UDMAP receive flow destination tag low byte selector configuration to be 120568608b5eSPeter Ujfalusi * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 120668608b5eSPeter Ujfalusi * the UDMAP section of the TRM for more information on this setting. 120768608b5eSPeter Ujfalusi * 120868608b5eSPeter Ujfalusi * @rx_fdq0_sz0_qnum: 120968608b5eSPeter Ujfalusi * UDMAP receive flow free descriptor queue 0 configuration to be programmed 121068608b5eSPeter Ujfalusi * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 121168608b5eSPeter Ujfalusi * UDMAP section of the TRM for more information on this setting. The specified 121268608b5eSPeter Ujfalusi * free queue must be valid within the Navigator Subsystem and must be owned 121368608b5eSPeter Ujfalusi * by the host, or a subordinate of the host, requesting allocation and 121468608b5eSPeter Ujfalusi * configuration of the receive flow. 121568608b5eSPeter Ujfalusi * 121668608b5eSPeter Ujfalusi * @rx_fdq1_qnum: 121768608b5eSPeter Ujfalusi * UDMAP receive flow free descriptor queue 1 configuration to be programmed 121868608b5eSPeter Ujfalusi * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 121968608b5eSPeter Ujfalusi * UDMAP section of the TRM for more information on this setting. The specified 122068608b5eSPeter Ujfalusi * free queue must be valid within the Navigator Subsystem and must be owned 122168608b5eSPeter Ujfalusi * by the host, or a subordinate of the host, requesting allocation and 122268608b5eSPeter Ujfalusi * configuration of the receive flow. 122368608b5eSPeter Ujfalusi * 122468608b5eSPeter Ujfalusi * @rx_fdq2_qnum: 122568608b5eSPeter Ujfalusi * UDMAP receive flow free descriptor queue 2 configuration to be programmed 122668608b5eSPeter Ujfalusi * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 122768608b5eSPeter Ujfalusi * UDMAP section of the TRM for more information on this setting. The specified 122868608b5eSPeter Ujfalusi * free queue must be valid within the Navigator Subsystem and must be owned 122968608b5eSPeter Ujfalusi * by the host, or a subordinate of the host, requesting allocation and 123068608b5eSPeter Ujfalusi * configuration of the receive flow. 123168608b5eSPeter Ujfalusi * 123268608b5eSPeter Ujfalusi * @rx_fdq3_qnum: 123368608b5eSPeter Ujfalusi * UDMAP receive flow free descriptor queue 3 configuration to be programmed 123468608b5eSPeter Ujfalusi * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 123568608b5eSPeter Ujfalusi * UDMAP section of the TRM for more information on this setting. The specified 123668608b5eSPeter Ujfalusi * free queue must be valid within the Navigator Subsystem and must be owned 123768608b5eSPeter Ujfalusi * by the host, or a subordinate of the host, requesting allocation and 123868608b5eSPeter Ujfalusi * configuration of the receive flow. 123968608b5eSPeter Ujfalusi * 124068608b5eSPeter Ujfalusi * @rx_ps_location: 124168608b5eSPeter Ujfalusi * UDMAP receive flow PS words location configuration to be programmed into the 124268608b5eSPeter Ujfalusi * rx_ps_location field of the flow's RFLOW_RFA register. 124368608b5eSPeter Ujfalusi */ 124468608b5eSPeter Ujfalusi struct ti_sci_msg_rm_udmap_flow_cfg_req { 124568608b5eSPeter Ujfalusi struct ti_sci_msg_hdr hdr; 124668608b5eSPeter Ujfalusi u32 valid_params; 124768608b5eSPeter Ujfalusi u16 nav_id; 124868608b5eSPeter Ujfalusi u16 flow_index; 124968608b5eSPeter Ujfalusi u8 rx_einfo_present; 125068608b5eSPeter Ujfalusi u8 rx_psinfo_present; 125168608b5eSPeter Ujfalusi u8 rx_error_handling; 125268608b5eSPeter Ujfalusi u8 rx_desc_type; 125368608b5eSPeter Ujfalusi u16 rx_sop_offset; 125468608b5eSPeter Ujfalusi u16 rx_dest_qnum; 125568608b5eSPeter Ujfalusi u8 rx_src_tag_hi; 125668608b5eSPeter Ujfalusi u8 rx_src_tag_lo; 125768608b5eSPeter Ujfalusi u8 rx_dest_tag_hi; 125868608b5eSPeter Ujfalusi u8 rx_dest_tag_lo; 125968608b5eSPeter Ujfalusi u8 rx_src_tag_hi_sel; 126068608b5eSPeter Ujfalusi u8 rx_src_tag_lo_sel; 126168608b5eSPeter Ujfalusi u8 rx_dest_tag_hi_sel; 126268608b5eSPeter Ujfalusi u8 rx_dest_tag_lo_sel; 126368608b5eSPeter Ujfalusi u16 rx_fdq0_sz0_qnum; 126468608b5eSPeter Ujfalusi u16 rx_fdq1_qnum; 126568608b5eSPeter Ujfalusi u16 rx_fdq2_qnum; 126668608b5eSPeter Ujfalusi u16 rx_fdq3_qnum; 126768608b5eSPeter Ujfalusi u8 rx_ps_location; 126868608b5eSPeter Ujfalusi } __packed; 126968608b5eSPeter Ujfalusi 12701e407f33SSuman Anna /** 12711e407f33SSuman Anna * struct ti_sci_msg_req_proc_request - Request a processor 12721e407f33SSuman Anna * @hdr: Generic Header 12731e407f33SSuman Anna * @processor_id: ID of processor being requested 12741e407f33SSuman Anna * 12751e407f33SSuman Anna * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 12761e407f33SSuman Anna * message. 12771e407f33SSuman Anna */ 12781e407f33SSuman Anna struct ti_sci_msg_req_proc_request { 12791e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 12801e407f33SSuman Anna u8 processor_id; 12811e407f33SSuman Anna } __packed; 12821e407f33SSuman Anna 12831e407f33SSuman Anna /** 12841e407f33SSuman Anna * struct ti_sci_msg_req_proc_release - Release a processor 12851e407f33SSuman Anna * @hdr: Generic Header 12861e407f33SSuman Anna * @processor_id: ID of processor being released 12871e407f33SSuman Anna * 12881e407f33SSuman Anna * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 12891e407f33SSuman Anna * message. 12901e407f33SSuman Anna */ 12911e407f33SSuman Anna struct ti_sci_msg_req_proc_release { 12921e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 12931e407f33SSuman Anna u8 processor_id; 12941e407f33SSuman Anna } __packed; 12951e407f33SSuman Anna 12961e407f33SSuman Anna /** 12971e407f33SSuman Anna * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 12981e407f33SSuman Anna * @hdr: Generic Header 12991e407f33SSuman Anna * @processor_id: ID of processor being handed over 13001e407f33SSuman Anna * @host_id: Host ID the control needs to be transferred to 13011e407f33SSuman Anna * 13021e407f33SSuman Anna * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 13031e407f33SSuman Anna * message. 13041e407f33SSuman Anna */ 13051e407f33SSuman Anna struct ti_sci_msg_req_proc_handover { 13061e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 13071e407f33SSuman Anna u8 processor_id; 13081e407f33SSuman Anna u8 host_id; 13091e407f33SSuman Anna } __packed; 13101e407f33SSuman Anna 13111e407f33SSuman Anna /* Boot Vector masks */ 13121e407f33SSuman Anna #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 13131e407f33SSuman Anna #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 13141e407f33SSuman Anna #define TI_SCI_ADDR_HIGH_SHIFT 32 13151e407f33SSuman Anna 13161e407f33SSuman Anna /** 13171e407f33SSuman Anna * struct ti_sci_msg_req_set_config - Set Processor boot configuration 13181e407f33SSuman Anna * @hdr: Generic Header 13191e407f33SSuman Anna * @processor_id: ID of processor being configured 13201e407f33SSuman Anna * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 13211e407f33SSuman Anna * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 13221e407f33SSuman Anna * @config_flags_set: Optional Processor specific Config Flags to set. 13231e407f33SSuman Anna * Setting a bit here implies the corresponding mode 13241e407f33SSuman Anna * will be set 13251e407f33SSuman Anna * @config_flags_clear: Optional Processor specific Config Flags to clear. 13261e407f33SSuman Anna * Setting a bit here implies the corresponding mode 13271e407f33SSuman Anna * will be cleared 13281e407f33SSuman Anna * 13291e407f33SSuman Anna * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 13301e407f33SSuman Anna * message. 13311e407f33SSuman Anna */ 13321e407f33SSuman Anna struct ti_sci_msg_req_set_config { 13331e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 13341e407f33SSuman Anna u8 processor_id; 13351e407f33SSuman Anna u32 bootvector_low; 13361e407f33SSuman Anna u32 bootvector_high; 13371e407f33SSuman Anna u32 config_flags_set; 13381e407f33SSuman Anna u32 config_flags_clear; 13391e407f33SSuman Anna } __packed; 13401e407f33SSuman Anna 13411e407f33SSuman Anna /** 13421e407f33SSuman Anna * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags 13431e407f33SSuman Anna * @hdr: Generic Header 13441e407f33SSuman Anna * @processor_id: ID of processor being configured 13451e407f33SSuman Anna * @control_flags_set: Optional Processor specific Control Flags to set. 13461e407f33SSuman Anna * Setting a bit here implies the corresponding mode 13471e407f33SSuman Anna * will be set 13481e407f33SSuman Anna * @control_flags_clear:Optional Processor specific Control Flags to clear. 13491e407f33SSuman Anna * Setting a bit here implies the corresponding mode 13501e407f33SSuman Anna * will be cleared 13511e407f33SSuman Anna * 13521e407f33SSuman Anna * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK 13531e407f33SSuman Anna * message. 13541e407f33SSuman Anna */ 13551e407f33SSuman Anna struct ti_sci_msg_req_set_ctrl { 13561e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 13571e407f33SSuman Anna u8 processor_id; 13581e407f33SSuman Anna u32 control_flags_set; 13591e407f33SSuman Anna u32 control_flags_clear; 13601e407f33SSuman Anna } __packed; 13611e407f33SSuman Anna 13621e407f33SSuman Anna /** 13631e407f33SSuman Anna * struct ti_sci_msg_req_get_status - Processor boot status request 13641e407f33SSuman Anna * @hdr: Generic Header 13651e407f33SSuman Anna * @processor_id: ID of processor whose status is being requested 13661e407f33SSuman Anna * 13671e407f33SSuman Anna * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate 13681e407f33SSuman Anna * message, or NACK in case of inability to satisfy request. 13691e407f33SSuman Anna */ 13701e407f33SSuman Anna struct ti_sci_msg_req_get_status { 13711e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 13721e407f33SSuman Anna u8 processor_id; 13731e407f33SSuman Anna } __packed; 13741e407f33SSuman Anna 13751e407f33SSuman Anna /** 13761e407f33SSuman Anna * struct ti_sci_msg_resp_get_status - Processor boot status response 13771e407f33SSuman Anna * @hdr: Generic Header 13781e407f33SSuman Anna * @processor_id: ID of processor whose status is returned 13791e407f33SSuman Anna * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 13801e407f33SSuman Anna * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 13811e407f33SSuman Anna * @config_flags: Optional Processor specific Config Flags set currently 13821e407f33SSuman Anna * @control_flags: Optional Processor specific Control Flags set currently 13831e407f33SSuman Anna * @status_flags: Optional Processor specific Status Flags set currently 13841e407f33SSuman Anna * 13851e407f33SSuman Anna * Response structure to a TI_SCI_MSG_GET_STATUS request. 13861e407f33SSuman Anna */ 13871e407f33SSuman Anna struct ti_sci_msg_resp_get_status { 13881e407f33SSuman Anna struct ti_sci_msg_hdr hdr; 13891e407f33SSuman Anna u8 processor_id; 13901e407f33SSuman Anna u32 bootvector_low; 13911e407f33SSuman Anna u32 bootvector_high; 13921e407f33SSuman Anna u32 config_flags; 13931e407f33SSuman Anna u32 control_flags; 13941e407f33SSuman Anna u32 status_flags; 13951e407f33SSuman Anna } __packed; 13961e407f33SSuman Anna 1397aa276781SNishanth Menon #endif /* __TI_SCI_H */ 1398