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/openbmc/qemu/tcg/arm/
H A Dtcg-target-con-set.h19 C_O0_I4(r, r, rI, rI)
29 C_O1_I2(r, r, rI)
32 C_O1_I2(r, r, ri)
33 C_O1_I2(r, rI, r)
34 C_O1_I2(r, rI, rIK)
35 C_O1_I2(r, rI, rIN)
43 C_O1_I4(r, r, r, rI, rI)
/openbmc/qemu/tcg/i386/
H A Dtcg-target-con-set.h22 C_O0_I2(ri, r)
29 C_O0_I4(r, r, ri, ri)
42 C_O1_I2(r, 0, ri)
43 C_O1_I2(r, 0, rI)
47 C_O1_I2(r, r, ri)
56 C_O1_I4(r, r, r, ri, ri)
/openbmc/qemu/tests/tcg/plugins/
H A Dmem.c104 RegionInfo *ri = (RegionInfo *) counts->data; in plugin_exit() local
109 ri->region_address, in plugin_exit()
110 ri->reads, in plugin_exit()
111 ri->writes, in plugin_exit()
112 ri->seen_all ? "true" : "false"); in plugin_exit()
133 RegionInfo *ri; in update_region_info() local
139 ri = (RegionInfo *) g_hash_table_lookup(regions, &region); in update_region_info()
141 if (!ri) { in update_region_info()
142 ri = g_new0(RegionInfo, 1); in update_region_info()
143 ri->region_address = region; in update_region_info()
[all …]
/openbmc/qemu/target/arm/
H A Dcpregs-pmu.c22 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, in access_tpm() argument
260 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, in pmreg_access() argument
267 const ARMCPRegInfo *ri, in pmreg_access_pmcr() argument
274 const ARMCPRegInfo *ri, in pmreg_access_xevcntr() argument
285 return pmreg_access(env, ri, isread); in pmreg_access_xevcntr()
289 const ARMCPRegInfo *ri, in pmreg_access_swinc() argument
300 return pmreg_access(env, ri, isread); in pmreg_access_swinc()
304 const ARMCPRegInfo *ri, in pmreg_access_selr() argument
314 return pmreg_access(env, ri, isread); in pmreg_access_selr()
318 const ARMCPRegInfo *ri, in pmreg_access_ccntr() argument
[all …]
H A Dhelper.c43 uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) in raw_read() argument
45 assert(ri->fieldoffset); in raw_read()
46 if (cpreg_field_is_64bit(ri)) { in raw_read()
47 return CPREG_FIELD64(env, ri); in raw_read()
49 return CPREG_FIELD32(env, ri); in raw_read()
53 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in raw_write() argument
55 assert(ri->fieldoffset); in raw_write()
56 if (cpreg_field_is_64bit(ri)) { in raw_write()
57 CPREG_FIELD64(env, ri) = value; in raw_write()
59 CPREG_FIELD32(env, ri) = value; in raw_write()
[all …]
H A Dgdbstub.c244 const ARMCPRegInfo *ri; in arm_gdb_get_sysreg() local
248 ri = get_arm_cp_reginfo(cpu->cp_regs, key); in arm_gdb_get_sysreg()
249 if (ri) { in arm_gdb_get_sysreg()
250 if (cpreg_field_is_64bit(ri)) { in arm_gdb_get_sysreg()
251 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); in arm_gdb_get_sysreg()
253 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); in arm_gdb_get_sysreg()
266 ARMCPRegInfo *ri, uint32_t ri_key, in arm_gen_one_feature_sysreg() argument
269 gdb_feature_builder_append_reg(builder, ri->name, bitsize, n, in arm_gen_one_feature_sysreg()
279 ARMCPRegInfo *ri = value; in arm_register_sysreg_for_feature() local
285 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { in arm_register_sysreg_for_feature()
[all …]
H A Dcpregs.h1000 * ARMCPRegInfo *ri.
1002 #define CPREG_FIELD32(env, ri) \ argument
1003 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1004 #define CPREG_FIELD64(env, ri) \ argument
1005 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1063 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1066 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1068 /* CPReadFn that just reads the value from ri->fieldoffset */
1069 uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri);
1071 /* CPWriteFn that just writes the value to ri->fieldoffset */
[all …]
/openbmc/qemu/tcg/s390x/
H A Dtcg-target-con-set.h17 C_O0_I2(r, ri)
26 C_O1_I2(r, 0, ri)
27 C_O1_I2(r, 0, rI)
30 C_O1_I2(r, r, ri)
32 C_O1_I2(r, r, rI)
43 C_O1_I4(r, r, rC, rI, r)
/openbmc/phosphor-pid-control/test/
H A Dsensor_pluggable_unittest.cpp29 std::unique_ptr<ReadInterface> ri = std::make_unique<ReadInterfaceMock>(); in TEST() local
36 PluggableSensor p(name, timeout, std::move(ri), std::move(wi)); in TEST()
47 std::unique_ptr<ReadInterface> ri = std::make_unique<ReadInterfaceMock>(); in TEST() local
54 ReadInterfaceMock* rip = reinterpret_cast<ReadInterfaceMock*>(ri.get()); in TEST()
56 PluggableSensor p(name, timeout, std::move(ri), std::move(wi)); in TEST()
77 std::unique_ptr<ReadInterface> ri = std::make_unique<ReadInterfaceMock>(); in TEST() local
86 PluggableSensor p(name, timeout, std::move(ri), std::move(wi)); in TEST()
/openbmc/qemu/tcg/
H A Dtcg-op-vec.c230 TCGArg ri = tcgv_vec_arg(r); in tcg_gen_dup_i64_vec() local
231 TCGTemp *rt = arg_temp(ri); in tcg_gen_dup_i64_vec()
236 vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); in tcg_gen_dup_i64_vec()
240 vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah); in tcg_gen_dup_i64_vec()
243 vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); in tcg_gen_dup_i64_vec()
249 TCGArg ri = tcgv_vec_arg(r); in tcg_gen_dup_i32_vec() local
251 TCGTemp *rt = arg_temp(ri); in tcg_gen_dup_i32_vec()
254 vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai); in tcg_gen_dup_i32_vec()
260 TCGArg ri = tcgv_vec_arg(r); in tcg_gen_dup_mem_vec() local
262 TCGTemp *rt = arg_temp(ri); in tcg_gen_dup_mem_vec()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c560 static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_ap_read() argument
563 int regno = ri->opc2 & 3; in icv_ap_read()
564 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_read()
567 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_read()
571 static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_ap_write() argument
575 int regno = ri->opc2 & 3; in icv_ap_write()
576 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_write()
578 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_write()
589 static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_bpr_read() argument
592 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_read()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dop_helper.c764 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, key); in HELPER() local
769 assert(ri != NULL); in HELPER()
771 if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 in HELPER()
772 && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) { in HELPER()
777 if (ri->accessfn) { in HELPER()
778 res = ri->accessfn(env, ri, isread); in HELPER()
799 if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && in HELPER()
802 uint32_t mask = 1 << ri->crn; in HELPER()
804 if (ri->type & ARM_CP_64BIT) { in HELPER()
805 mask = 1 << ri->crm; in HELPER()
[all …]
H A Dcpregs-at.c199 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) in ats_write() argument
201 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats_write()
207 switch (ri->opc2 & 6) { in ats_write()
212 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
222 if (ri->crm == 9 && arm_pan_enabled(env)) { in ats_write()
268 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, in ats1h_write() argument
271 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; in ats1h_write()
281 static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, in at_e012_access() argument
297 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, in at_s1e2_access() argument
304 return at_e012_access(env, ri, isread); in at_s1e2_access()
[all …]
H A Dtlb-insns.c18 static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, in access_ttlb() argument
28 static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, in access_ttlbis() argument
39 static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, in access_ttlbos() argument
50 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_is_write() argument
58 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiasid_is_write() argument
66 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimva_is_write() argument
74 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimvaa_is_write() argument
92 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiall_write() argument
105 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbimva_write() argument
119 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, in tlbiasid_write() argument
[all …]
/openbmc/qemu/hw/misc/
H A Dimx7_src.c136 struct SRCSCRResetInfo *ri = data.host_ptr; in imx7_clear_reset_bit() local
137 IMX7SRCState *s = ri->s; in imx7_clear_reset_bit()
141 s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); in imx7_clear_reset_bit()
145 g_free(ri); in imx7_clear_reset_bit()
152 struct SRCSCRResetInfo *ri; in imx7_defer_clear_reset_bit() local
159 ri = g_new(struct SRCSCRResetInfo, 1); in imx7_defer_clear_reset_bit()
160 ri->s = s; in imx7_defer_clear_reset_bit()
161 ri->reset_bit = reset_shift; in imx7_defer_clear_reset_bit()
163 async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); in imx7_defer_clear_reset_bit()
H A Dimx6_src.c120 struct SRCSCRResetInfo *ri = data.host_ptr; in imx6_clear_reset_bit() local
121 IMX6SRCState *s = ri->s; in imx6_clear_reset_bit()
125 s->regs[SRC_SCR] = deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0); in imx6_clear_reset_bit()
128 g_free(ri); in imx6_clear_reset_bit()
135 struct SRCSCRResetInfo *ri; in imx6_defer_clear_reset_bit() local
142 ri = g_new(struct SRCSCRResetInfo, 1); in imx6_defer_clear_reset_bit()
143 ri->s = s; in imx6_defer_clear_reset_bit()
144 ri->reset_bit = reset_shift; in imx6_defer_clear_reset_bit()
146 async_run_on_cpu(cpu, imx6_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); in imx6_defer_clear_reset_bit()
/openbmc/qemu/tcg/ppc/
H A Dtcg-target-con-set.h25 C_O1_I2(r, rI, r)
27 C_O1_I2(r, r, ri)
29 C_O1_I2(r, r, rI)
34 C_O1_I2(r, rI, rN)
/openbmc/phosphor-pid-control/sensors/
H A Dbuilder.cpp58 std::unique_ptr<ReadInterface> ri; in buildSensors() local
86 ri = DbusPassive::createDbusPassive( in buildSensors()
93 ri = DbusPassive::createDbusPassive( in buildSensors()
98 if (ri == nullptr) in buildSensors()
109 ri = std::make_unique<SysFsRead>(info->readPath); in buildSensors()
112 ri = std::make_unique<WriteOnly>(); in buildSensors()
161 name, info->timeout, std::move(ri), std::move(wi), in buildSensors()
190 name, info->timeout, std::move(ri), std::move(wi), in buildSensors()
/openbmc/qemu/tcg/riscv/
H A Dtcg-target-con-set.h17 C_O1_I2(r, r, ri)
18 C_O1_I2(r, r, rI)
20 C_O1_I4(r, r, rI, rM, rM)
/openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/
H A DDINF.interface.yaml8 - name: RI
11 RI keyword. Power resource ID.
/openbmc/qemu/hw/core/
H A Dregister.c240 int num, RegisterInfo *ri, in register_init_block() argument
259 RegisterInfo *r = &ri[index]; in register_init_block()
281 int num, RegisterInfo *ri, in register_init_block8() argument
287 return register_init_block(owner, rae, num, ri, (void *) in register_init_block8()
293 int num, RegisterInfo *ri, in register_init_block32() argument
299 return register_init_block(owner, rae, num, ri, (void *) in register_init_block32()
305 int num, RegisterInfo *ri, in register_init_block64() argument
311 return register_init_block(owner, rae, num, ri, (void *) in register_init_block64()
/openbmc/openbmc/poky/meta/recipes-devtools/ruby/
H A Druby_3.4.3.bb124 PACKAGES =+ "${PN}-ri-docs ${PN}-rdoc"
126 SUMMARY:${PN}-ri-docs = "ri (Ruby Interactive) documentation for the Ruby standard library"
127 RDEPENDS:${PN}-ri-docs = "${PN}"
128 FILES:${PN}-ri-docs += "${datadir}/ri"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-dbs/leveldb/leveldb/
H A D0001-CMakeLists.txt-fix-googletest-related-options.patch13 $ grep -Ri install_.*mock .
16 $ grep -Ri build_gmock .
21 $ grep -Ri install_gtest .
/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Dsnps-dw-apb-uart.txt36 - ri-override : Override the RI modem status signal. This signal will always be
52 ri-override;
/openbmc/qemu/tcg/mips/
H A Dtcg-target-con-set.h20 C_O1_I2(r, r, ri)
21 C_O1_I2(r, r, rI)

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