Lines Matching full:ri
43 uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
45 assert(ri->fieldoffset);
46 if (cpreg_field_is_64bit(ri)) {
47 return CPREG_FIELD64(env, ri);
49 return CPREG_FIELD32(env, ri);
53 void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
55 assert(ri->fieldoffset);
56 if (cpreg_field_is_64bit(ri)) {
57 CPREG_FIELD64(env, ri) = value;
59 CPREG_FIELD32(env, ri) = value;
63 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
65 return (char *)env + ri->fieldoffset;
68 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
71 if (ri->type & ARM_CP_CONST) {
72 return ri->resetvalue;
73 } else if (ri->raw_readfn) {
74 return ri->raw_readfn(env, ri);
75 } else if (ri->readfn) {
76 return ri->readfn(env, ri);
78 return raw_read(env, ri);
82 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
91 if (ri->type & ARM_CP_CONST) {
93 } else if (ri->raw_writefn) {
94 ri->raw_writefn(env, ri, v);
95 } else if (ri->writefn) {
96 ri->writefn(env, ri, v);
98 raw_write(env, ri, v);
102 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
116 if ((ri->type & ARM_CP_CONST) ||
117 ri->fieldoffset ||
118 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
132 const ARMCPRegInfo *ri;
135 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
136 if (!ri) {
140 if (ri->type & ARM_CP_NO_RAW) {
144 newval = read_raw_cp_reg(&cpu->env, ri);
158 write_raw_cp_reg(&cpu->env, ri, oldval);
159 if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
163 write_raw_cp_reg(&cpu->env, ri, newval);
178 const ARMCPRegInfo *ri;
180 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
181 if (!ri) {
185 if (ri->type & ARM_CP_NO_RAW) {
193 write_raw_cp_reg(&cpu->env, ri, v);
194 if (read_raw_cp_reg(&cpu->env, ri) != v) {
205 const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
207 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
217 const ARMCPRegInfo *ri;
219 ri = g_hash_table_lookup(cpu->cp_regs, key);
221 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
287 const ARMCPRegInfo *ri,
304 const ARMCPRegInfo *ri,
321 CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
334 static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
344 static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
353 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
357 raw_write(env, ri, value);
361 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
365 if (raw_read(env, ri) != value) {
371 raw_write(env, ri, value);
375 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
380 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
389 raw_write(env, ri, value);
524 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
573 static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
589 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
595 cpacr_write(env, ri, 0);
598 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
616 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
672 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
682 raw_write(env, ri, value & ~0x1FULL);
685 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
787 static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
793 scr_write(env, ri, 0);
797 const ARMCPRegInfo *ri,
808 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
817 ri->secure & ARM_CP_SECSTATE_S);
822 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
825 raw_write(env, ri, value & 0xf);
828 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
877 static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
887 static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
891 return access_aa64_tid1(env, ri, isread);
983 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
990 static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1004 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1010 return teecr_access(env, ri, isread);
1068 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1092 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1197 const ARMCPRegInfo *ri,
1204 const ARMCPRegInfo *ri,
1210 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1216 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1223 const ARMCPRegInfo *ri,
1254 const ARMCPRegInfo *ri,
1481 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1489 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1495 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1501 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1516 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1533 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1542 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1564 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1566 gt_timer_reset(env, ri, GTIMER_PHYS);
1569 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1572 gt_cval_write(env, ri, GTIMER_PHYS, value);
1575 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1577 return gt_tval_read(env, ri, GTIMER_PHYS);
1580 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1583 gt_tval_write(env, ri, GTIMER_PHYS, value);
1586 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1589 gt_ctl_write(env, ri, GTIMER_PHYS, value);
1617 const ARMCPRegInfo *ri)
1623 static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1627 gt_cval_write(env, ri, timeridx, value);
1631 const ARMCPRegInfo *ri)
1634 return gt_tval_read(env, ri, timeridx);
1637 static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1641 gt_tval_write(env, ri, timeridx, value);
1645 const ARMCPRegInfo *ri)
1651 static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1655 gt_ctl_write(env, ri, timeridx, value);
1658 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1660 gt_timer_reset(env, ri, GTIMER_VIRT);
1663 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1666 gt_cval_write(env, ri, GTIMER_VIRT, value);
1669 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1681 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1688 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1691 gt_ctl_write(env, ri, GTIMER_VIRT, value);
1694 static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1728 raw_write(env, ri, value);
1737 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1743 raw_write(env, ri, value);
1748 const ARMCPRegInfo *ri)
1754 static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1758 gt_cval_write(env, ri, timeridx, value);
1762 const ARMCPRegInfo *ri)
1765 return gt_tval_read(env, ri, timeridx);
1768 static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1772 gt_tval_write(env, ri, timeridx, value);
1776 const ARMCPRegInfo *ri)
1782 static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1786 gt_ctl_write(env, ri, timeridx, value);
1789 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1791 gt_timer_reset(env, ri, GTIMER_HYP);
1794 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1797 gt_cval_write(env, ri, GTIMER_HYP, value);
1800 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1802 return gt_tval_read(env, ri, GTIMER_HYP);
1805 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1808 gt_tval_write(env, ri, GTIMER_HYP, value);
1811 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1814 gt_ctl_write(env, ri, GTIMER_HYP, value);
1817 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1819 gt_timer_reset(env, ri, GTIMER_SEC);
1822 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1825 gt_cval_write(env, ri, GTIMER_SEC, value);
1828 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1830 return gt_tval_read(env, ri, GTIMER_SEC);
1833 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1836 gt_tval_write(env, ri, GTIMER_SEC, value);
1839 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1842 gt_ctl_write(env, ri, GTIMER_SEC, value);
1845 static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1847 gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS);
1850 static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1853 gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value);
1856 static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1858 return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS);
1861 static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1864 gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value);
1867 static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1870 gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value);
1873 static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1875 gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT);
1878 static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1881 gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value);
1884 static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1886 return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT);
1889 static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1892 gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value);
1895 static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1898 gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value);
1901 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1903 gt_timer_reset(env, ri, GTIMER_HYPVIRT);
1906 static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1909 gt_cval_write(env, ri, GTIMER_HYPVIRT, value);
1912 static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1914 return gt_tval_read(env, ri, GTIMER_HYPVIRT);
1917 static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1920 gt_tval_write(env, ri, GTIMER_HYPVIRT, value);
1923 static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1926 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value);
2205 const ARMCPRegInfo *ri,
2215 static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
2221 raw_write(env, ri, value);
2240 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2280 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2283 raw_write(env, ri, value);
2285 raw_write(env, ri, value & 0xfffff6ff);
2287 raw_write(env, ri, value & 0xfffff1ff);
2321 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2327 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2332 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2338 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2343 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2345 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2355 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2359 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2370 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2383 raw_write(env, ri, value);
2386 static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2395 static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
2400 static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2409 static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
2414 static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2430 static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2439 static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
2444 static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2453 static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
2458 static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2479 static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2494 static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2510 static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri,
2514 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
2515 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
2519 if (ri->opc1 & 4) {
2523 if (ri->opc2 & 0x1) {
2532 if (ri->opc2 & 0x1) {
2540 static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri)
2543 uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
2544 (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
2546 if (ri->opc1 & 4) {
2550 if (ri->opc2 & 0x1) {
2559 if (ri->opc2 & 0x1) {
2680 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2711 raw_write(env, ri, value);
2714 static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
2721 raw_write(env, ri, value);
2724 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2728 if (cpreg_field_is_64bit(ri) &&
2729 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
2733 raw_write(env, ri, value);
2736 static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2745 if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
2752 raw_write(env, ri, value);
2755 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2765 if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
2768 raw_write(env, ri, value);
2847 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2862 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2869 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2920 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3015 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
3022 return raw_read(env, ri);
3044 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
3084 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
3089 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3095 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
3100 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3106 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
3115 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
3121 static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri)
3126 static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri,
3139 static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri)
3144 static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri,
3157 static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri)
3162 static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri,
3175 static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri)
3180 static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
3194 const ARMCPRegInfo *ri,
3235 static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
3241 static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
3247 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
3275 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3287 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3300 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3305 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3310 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3322 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
3323 if (ri->opc1 == 6) { /* SCTLR_EL3 */
3331 if (raw_read(env, ri) == value) {
3339 raw_write(env, ri, value);
3344 if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) {
3355 static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
3374 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3378 mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
3381 static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3400 static CPAccessResult access_nv1(CPUARMState *env, const ARMCPRegInfo *ri,
3423 static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri,
3772 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3777 static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
3785 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
3793 static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3796 hcr_write(env, ri, 0);
3905 static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
3950 static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri,
3998 static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4013 static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
4217 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri,
4289 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
4389 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
4402 static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
4411 return e2h_access(env, ri, isread);
4414 static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
4423 return e2h_access(env, ri, isread);
4432 static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
4438 ri = ri->opaque;
4439 readfn = ri->readfn;
4441 readfn = ri->orig_readfn;
4446 return readfn(env, ri);
4449 static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
4456 ri = ri->opaque;
4457 writefn = ri->writefn;
4459 writefn = ri->orig_writefn;
4464 writefn(env, ri, value);
4467 static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri)
4469 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
4470 return ri->orig_readfn(env, ri->opaque);
4473 static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri,
4476 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
4477 return ri->orig_writefn(env, ri->opaque, value);
4481 const ARMCPRegInfo *ri,
4497 if (ri->orig_accessfn) {
4498 return ri->orig_accessfn(env, ri->opaque, isread);
4657 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4694 static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
4708 static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4721 static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
4922 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4931 raw_write(env, ri, value & 0xf);
4962 static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,
4982 static CPAccessResult access_smprimap(CPUARMState *env, const ARMCPRegInfo *ri,
4994 static CPAccessResult access_smpri(CPUARMState *env, const ARMCPRegInfo *ri,
5044 static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
5050 static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
5063 raw_write(env, ri, value);
5130 static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
5141 static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
5169 static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri,
5175 static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri)
5181 const ARMCPRegInfo *ri, bool isread)
5207 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
5218 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
5235 const ARMCPRegInfo *ri, bool isread)
5249 const ARMCPRegInfo *ri, bool isread)
5255 return access_lor_ns(env, ri, isread);
5291 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
5362 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
5379 ri->name, error_get_pretty(err));
5450 static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
5460 static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
5478 static CPAccessResult access_tfsr_el1(CPUARMState *env, const ARMCPRegInfo *ri,
5481 CPAccessResult nv1 = access_nv1(env, ri, isread);
5486 return access_mte(env, ri, isread);
5489 static CPAccessResult access_tfsr_el2(CPUARMState *env, const ARMCPRegInfo *ri,
5518 static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
5523 static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
5662 static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
5690 const ARMCPRegInfo *ri,
5693 CPAccessResult nv1 = access_nv1(env, ri, isread);
5698 return access_scxtnum(env, ri, isread);
5723 static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
5761 static void vncr_write(CPUARMState *env, const ARMCPRegInfo *ri,
5783 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
5832 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
5835 return extract64(ccsidr_read(env, ri), 32, 32);
5846 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
5856 static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
5860 return access_aa64_tid3(env, ri, isread);
5866 static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
5877 const ARMCPRegInfo *ri, bool isread)
7684 for (size_t ri = 0; ri < regs_len; ++ri) {
7685 ARMCPRegInfo *r = regs + ri;
7711 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
7717 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)