Lines Matching full:ri
560 static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_ap_read() argument
563 int regno = ri->opc2 & 3; in icv_ap_read()
564 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_read()
567 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_read()
571 static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_ap_write() argument
575 int regno = ri->opc2 & 3; in icv_ap_write()
576 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_write()
578 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_write()
589 static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_bpr_read() argument
592 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_read()
609 trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icv_bpr_read()
614 static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_bpr_write() argument
618 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_write()
620 trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, in icv_bpr_write()
633 static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_pmr_read() argument
645 static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_pmr_write() argument
660 static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_igrpen_read() argument
666 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_read()
669 trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_read()
674 static void icv_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_igrpen_write() argument
680 trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_write()
683 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_write()
689 static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_ctlr_read() argument
712 static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_ctlr_write() argument
727 static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_rpr_read() argument
740 static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_hppir_read() argument
743 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_hppir_read()
760 trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1, in icv_hppir_read()
800 static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_iar_read() argument
803 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_iar_read()
836 trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, in icv_iar_read()
844 static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) in icv_nmiar1_read() argument
1104 static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_pmr_read() argument
1110 return icv_pmr_read(env, ri); in icc_pmr_read()
1131 static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_pmr_write() argument
1137 return icv_pmr_write(env, ri, value); in icc_pmr_write()
1262 static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_iar0_read() argument
1268 return icv_iar_read(env, ri); in icc_iar0_read()
1285 static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_iar1_read() argument
1292 return icv_iar_read(env, ri); in icc_iar1_read()
1313 static uint64_t icc_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_nmiar1_read() argument
1319 return icv_nmiar1_read(env, ri); in icc_nmiar1_read()
1551 static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_dir_write() argument
1584 static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, in icv_eoir_write() argument
1590 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_eoir_write()
1594 trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, in icv_eoir_write()
1645 static void icc_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_eoir_write() argument
1652 bool is_eoir0 = ri->crm == 8; in icc_eoir_write()
1655 icv_eoir_write(env, ri, value); in icc_eoir_write()
1716 static uint64_t icc_hppir0_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_hppir0_read() argument
1722 return icv_hppir_read(env, ri); in icc_hppir0_read()
1730 static uint64_t icc_hppir1_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_hppir1_read() argument
1736 return icv_hppir_read(env, ri); in icc_hppir1_read()
1744 static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_bpr_read() argument
1747 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; in icc_bpr_read()
1752 return icv_bpr_read(env, ri); in icc_bpr_read()
1780 trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icc_bpr_read()
1785 static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_bpr_write() argument
1789 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; in icc_bpr_write()
1793 icv_bpr_write(env, ri, value); in icc_bpr_write()
1797 trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1, in icc_bpr_write()
1827 static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_ap_read() argument
1832 int regno = ri->opc2 & 3; in icc_ap_read()
1833 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; in icc_ap_read()
1836 return icv_ap_read(env, ri); in icc_ap_read()
1845 trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icc_ap_read()
1849 static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_ap_write() argument
1854 int regno = ri->opc2 & 3; in icc_ap_write()
1855 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; in icc_ap_write()
1858 icv_ap_write(env, ri, value); in icc_ap_write()
1862 trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icc_ap_write()
1885 static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_dir_write() argument
1895 icv_dir_write(env, ri, value); in icc_dir_write()
1968 static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_rpr_read() argument
1974 return icv_rpr_read(env, ri); in icc_rpr_read()
2064 static void icc_sgi0r_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_sgi0r_write() argument
2074 static void icc_sgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_sgi1r_write() argument
2086 static void icc_asgi1r_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_asgi1r_write() argument
2100 static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_igrpen_read() argument
2103 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_read()
2107 return icv_igrpen_read(env, ri); in icc_igrpen_read()
2115 trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_read()
2120 static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_igrpen_write() argument
2124 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_write()
2127 icv_igrpen_write(env, ri, value); in icc_igrpen_write()
2131 trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_write()
2142 static uint64_t icc_igrpen1_el3_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_igrpen1_el3_read() argument
2153 static void icc_igrpen1_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_igrpen1_el3_write() argument
2166 static uint64_t icc_ctlr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_ctlr_el1_read() argument
2173 return icv_ctlr_read(env, ri); in icc_ctlr_el1_read()
2181 static void icc_ctlr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_ctlr_el1_write() argument
2189 icv_ctlr_write(env, ri, value); in icc_ctlr_el1_write()
2213 static uint64_t icc_ctlr_el3_read(CPUARMState *env, const ARMCPRegInfo *ri) in icc_ctlr_el3_read() argument
2236 static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, in icc_ctlr_el3_write() argument
2270 const ARMCPRegInfo *ri, bool isread) in gicv3_irqfiq_access() argument
2307 const ARMCPRegInfo *ri, bool isread) in gicv3_dir_access() argument
2317 return gicv3_irqfiq_access(env, ri, isread); in gicv3_dir_access()
2321 const ARMCPRegInfo *ri, bool isread) in gicv3_sgi_access() argument
2329 return gicv3_irqfiq_access(env, ri, isread); in gicv3_sgi_access()
2333 const ARMCPRegInfo *ri, bool isread) in gicv3_fiq_access() argument
2369 const ARMCPRegInfo *ri, bool isread) in gicv3_irq_access() argument
2404 static void icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) in icc_reset() argument
2686 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_ap_read() argument
2689 int regno = ri->opc2 & 3; in ich_ap_read()
2690 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in ich_ap_read()
2694 trace_gicv3_ich_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in ich_ap_read()
2698 static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, in ich_ap_write() argument
2702 int regno = ri->opc2 & 3; in ich_ap_write()
2703 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in ich_ap_write()
2705 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in ich_ap_write()
2715 static uint64_t ich_hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_hcr_read() argument
2724 static void ich_hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in ich_hcr_write() argument
2741 static uint64_t ich_vmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_vmcr_read() argument
2750 static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, in ich_vmcr_write() argument
2772 static uint64_t ich_lr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_lr_read() argument
2775 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_read()
2783 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2784 if (ri->crm >= 14) { in ich_lr_read()
2799 static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri, in ich_lr_write() argument
2803 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_write()
2810 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2811 if (ri->crm >= 14) { in ich_lr_write()
2837 static uint64_t ich_vtr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_vtr_read() argument
2856 static uint64_t ich_misr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_misr_read() argument
2865 static uint64_t ich_eisr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_eisr_read() argument
2874 static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) in ich_elrsr_read() argument
3044 * So instead we define the regs with no ri->opaque info, and in gicv3_init_cpuif()