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/openbmc/linux/Documentation/hwmon/
H A Dbcm54140.rst1 .. SPDX-License-Identifier: GPL-2.0-only
3 Broadcom BCM54140 Quad SGMII/QSGMII PHY
15 -----------
17 The Broadcom BCM54140 is a Quad SGMII/QSGMII PHY which supports monitoring
21 Both voltages and the temperature are measured in a round-robin fashion.
24 -------------
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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/openbmc/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
12 #include "emac-mac.h"
13 #include "emac-phy.h"
14 #include "emac-sgmii.h"
176 /* SGMII v2 per lane registers */
179 /* SGMII v2 PHY common registers */
183 /* SGMII v2 PHY registers per lane */
225 u64 rx_sz_65_127; /* packets that are 65-127 bytes */
226 u64 rx_sz_128_255; /* packets that are 128-255 bytes */
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/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
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/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
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/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME2 --------
7 ------------------
8 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
9 processor cores with high-performance data path acceleration architecture
14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
16 - Interconnect CoreNet platform
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
19 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
21 - Packet parsing, classification, and distribution
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/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
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/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
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/openbmc/linux/drivers/net/phy/
H A Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
80 * T = 413.35 - (0.49055 * bits[9:0])
82 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
83 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
119 * pin choses between 4x SGMII and QSGMII mode:
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
61 Currently tested with mpc866ads and mpc8349e-mitx.
88 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
89 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
97 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
107 Currently supports the Asix Electronics PHY found in the X-Surf 100
124 Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
223 Support for the Marvell 88Q2XXX 100/1000BASE-T1 Automotive Ethernet
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/openbmc/linux/Documentation/networking/
H A Dphy.rst26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
205 RGMII, and SGMII. See "PHY interface mode" below. For a full
[all …]
/openbmc/u-boot/board/freescale/p2041rdb/
H A DREADME4 with high-performance datapath acceleration architecture(DPAA), CoreNet
9 P2041RDB board is a quad core platform supporting the P2041 processor
19 => tftp 1000000 u-boot.bin
36 5. Change DIP-switch
37 SW1[1-5] = 10110
48 SDCard which contains RCW and U-Boot image.
59 5. Change DIP-switch
60 SW1[1-5] = 01100
71 SPI flash which contains RCW and U-Boot image.
84 5. Change DIP-switch
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/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-puzzle-m801.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Device Tree file for IEI Puzzle-M801
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/leds/common.h>
15 model = "IEI-Puzzle-M801";
16 compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806";
28 stdout-path = "serial0:115200n8";
37 v_3_3: regulator-3-3v {
38 compatible = "regulator-fixed";
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H A Darmada-7040-db.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-7040.dtsi"
13 compatible = "marvell,armada7040-db", "marvell,armada7040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
31 cp0_exp_usb3_0_current_regulator: gpio-regulator {
32 compatible = "regulator-gpio";
33 regulator-name = "cp0-usb3-0-current-regulator";
34 regulator-type = "current";
[all …]
H A Darmada-8040-mcbin.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15 "marvell,armada-ap806-quad", "marvell,armada-ap806";
18 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
37 regulator-min-microvolt = <3300000>;
[all …]
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-7040-db.dts4 * This file is dual-licensed: you can use it either under the terms
48 #include "armada-7040.dtsi"
52 compatible = "marvell,armada7040-db", "marvell,armada7040",
53 "marvell,armada-ap806-quad", "marvell,armada-ap806";
56 stdout-path = "serial0:115200n8";
72 * SDIO [0-5]
76 pin-func = < 1 1 1 1 1 1 0 0 0 0
90 pinctrl-names = "default";
91 pinctrl-0 = <&cpm_i2c0_pins>;
93 clock-frequency = <100000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi"
16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
38 stdout-path = "serial0:115200n8";
46 sys_mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <25000000>;
[all …]
/openbmc/linux/include/linux/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
79 * Set phydev->irq to PHY_POLL if interrupts are not supported,
83 #define PHY_POLL -1
84 #define PHY_MAC_INTERRUPT -2
93 * enum phy_interface_t - Interface Mode definitions
95 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
97 * @PHY_INTERFACE_MODE_MII: Media-independent interface
98 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
99 * @PHY_INTERFACE_MODE_SGMII: Serial gigabit media-independent interface
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x()
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw()
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/openbmc/linux/
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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