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/openbmc/u-boot/drivers/pwm/
H A DKconfig17 supports a programmable period and duty cycle. A 32-bit counter is
26 programmable period and duty cycle. A 32-bit counter is used.
43 four channels with a programmable period and duty cycle. Only a
52 programmable period and duty cycle. A 16-bit counter is used.
/openbmc/u-boot/doc/
H A DREADME.atmel_pmecc1 How to enable PMECC(Programmable Multibit ECC) for nand on Atmel SoCs
5 The Programmable Multibit ECC (PMECC) controller is a programmable binary
30 How to enable PMECC header for direct programmable boot.bin
H A DREADME.fsl-trustzone-components24 - Supports 8 fully programmable address regions, initially inactive at reset,
H A DREADME.N121354 - Programmable data endian control.
/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dcontrol.hpp47 Programmable, enumerator
89 {ImplementationType::Programmable, "Programmable"},
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pmc.h45 u32 pck[4]; /* 0x40 Programmable Clock Register 0 - 3 */
178 #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
179 #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
180 #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
181 #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
253 #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
254 #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
255 #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
256 #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
/openbmc/u-boot/drivers/mtd/nand/raw/
H A DKconfig32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Inventory/Item/
H A DDimm.interface.yaml150 Electrically Erasable Programmable Read Only Memory.
153 Flash Erasable Programmable Read Only Memory.
156 Erasable Programmable Read Only Memory.
/openbmc/qemu/docs/system/openrisc/
H A Dcpu-features.rst10 - Programmable Interrupt Controller (PIC)
/openbmc/qemu/include/hw/nvram/
H A Daspeed_otp.h2 * ASPEED OTP (One-Time Programmable) memory
H A Dbcm2835_otp.h2 * BCM2835 One-Time Programmable (OTP) Memory
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig115 and an optional customer programmable secure boot.
133 programmable secure boot.
/openbmc/u-boot/drivers/serial/
H A Dserial_mvebu_a3700.c80 * Set Programmable Oversampling Stack to 0, in mvebu_serial_setbrg()
156 * Set Programmable Oversampling Stack to 0, in _debug_uart_init()
/openbmc/u-boot/include/dt-bindings/clock/
H A Dat91.h17 #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
/openbmc/u-boot/arch/x86/include/asm/arch-qemu/
H A Dqemu.h9 /* Programmable Attribute Map (PAM) Registers */
/openbmc/openbmc/poky/meta/recipes-support/bash-completion/
H A Dbash-completion_2.16.0.bb1 SUMMARY = "Programmable Completion for Bash 4"
/openbmc/u-boot/drivers/video/stm32/
H A Dstm32_ltdc.c97 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
100 #define GC1R_TP BIT(25) /* Timing Programmable */
101 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
102 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
103 #define GC1R_DWP BIT(28) /* Dither Width Programmable */
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst5 processing system (PS) and AMD programmable logic (PL) in a single device.
/openbmc/u-boot/include/mtd/
H A Dmtd-abi.h168 /* Set OTP (One-Time Programmable) mode (factory vs. user) */
170 /* Get number of OTP (One-Time Programmable) regions */
172 /* Get all OTP (One-Time Programmable) info about MTD */
/openbmc/u-boot/include/linux/
H A Dserial_reg.h187 * These are the definitions for the Programmable Trigger Register
209 #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
211 #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
212 #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
381 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME49 . programmable interrupt controller (PIC)
58 . Enhanced programmable interrupt controller (EPIC)
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_83xx.h138 * Integrated Programmable Interrupt Controller
635 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
689 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
724 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
769 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
813 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
853 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
889 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
/openbmc/qemu/include/hw/misc/
H A Dsifive_u_otp.h2 * QEMU SiFive U OTP (One-Time Programmable) Memory interface
/openbmc/qemu/include/hw/arm/
H A Dmsf2-soc.h43 * System timer consists of two programmable 32-bit
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-shells/tcsh/
H A Dtcsh_6.24.12.bb4 programmable word completion, spelling correction and more."

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