| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| H A D | base.c | 32 struct nvkm_pmu *pmu = device->pmu; in nvkm_pmu_fan_controlled() local
34 /* Internal PMU FW does not currently control fans in any way, in nvkm_pmu_fan_controlled()
37 if (pmu && pmu->func->code.size) in nvkm_pmu_fan_controlled()
40 /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi in nvkm_pmu_fan_controlled()
48 nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) in nvkm_pmu_pgob() argument
50 if (pmu && pmu->func->pgob) in nvkm_pmu_pgob()
51 pmu->func->pgob(pmu, enable); in nvkm_pmu_pgob()
57 struct nvkm_pmu *pmu = container_of(work, typeof(*pmu), recv.work); in nvkm_pmu_recv() local
58 return pmu->func->recv(pmu); in nvkm_pmu_recv()
62 nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in nvkm_pmu_send() argument
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| H A D | gm20b.c | 28 #include <nvfw/pmu.h>
42 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon); in gm20b_pmu_acr_bootstrap_falcon() local
52 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_bootstrap_falcon()
54 &pmu->subdev, msecs_to_jiffies(1000)); in gm20b_pmu_acr_bootstrap_falcon()
129 struct nvkm_pmu *pmu = priv; in gm20b_pmu_acr_init_wpr_callback() local
130 struct nvkm_subdev *subdev = &pmu->subdev; in gm20b_pmu_acr_init_wpr_callback()
139 complete_all(&pmu->wpr_ready); in gm20b_pmu_acr_init_wpr_callback()
144 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu) in gm20b_pmu_acr_init_wpr() argument
154 return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, in gm20b_pmu_acr_init_wpr()
155 gm20b_pmu_acr_init_wpr_callback, pmu, 0); in gm20b_pmu_acr_init_wpr()
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| H A D | gt215.c | 30 gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], in gt215_pmu_send() argument
33 struct nvkm_subdev *subdev = &pmu->subdev; in gt215_pmu_send()
37 mutex_lock(&pmu->send.mutex); in gt215_pmu_send()
45 mutex_unlock(&pmu->send.mutex); in gt215_pmu_send()
50 * on a synchronous reply, take the PMU mutex and tell the in gt215_pmu_send()
54 pmu->recv.message = message; in gt215_pmu_send()
55 pmu->recv.process = process; in gt215_pmu_send()
65 pmu->send.base)); in gt215_pmu_send()
77 wait_event(pmu->recv.wait, (pmu->recv.process == 0)); in gt215_pmu_send()
78 reply[0] = pmu->recv.data[0]; in gt215_pmu_send()
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| H A D | gk20a.c | 51 gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state) in gk20a_pmu_dvfs_target() argument
53 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_target()
59 gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) in gk20a_pmu_dvfs_get_cur_state() argument
61 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_cur_state()
67 gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, in gk20a_pmu_dvfs_get_target_state() argument
70 struct gk20a_pmu_dvfs_data *data = pmu->data; in gk20a_pmu_dvfs_get_target_state()
71 struct nvkm_clk *clk = pmu->base.subdev.device->clk; in gk20a_pmu_dvfs_get_target_state()
86 nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n", in gk20a_pmu_dvfs_get_target_state()
95 gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, in gk20a_pmu_dvfs_get_dev_status() argument
98 struct nvkm_falcon *falcon = &pmu->base.falcon; in gk20a_pmu_dvfs_get_dev_status()
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| /openbmc/linux/tools/perf/util/ |
| H A D | pmus.c | 17 #include "pmu.h"
21 * core_pmus: A PMU belongs to core_pmus if it's name is "cpu" or it's sysfs
23 * must have pmu->is_core=1. If there are more than one PMU in
26 * homogeneous PMU, and thus they are treated as homogeneous
29 * matter whether PMU is present per SMT-thread or outside of the
33 * must have pmu->is_core=0 but pmu->is_uncore could be 0 or 1.
67 struct perf_pmu *pmu, *tmp; in perf_pmus__destroy() local
69 list_for_each_entry_safe(pmu, tmp, &core_pmus, list) { in perf_pmus__destroy()
70 list_del(&pmu->list); in perf_pmus__destroy()
72 perf_pmu__delete(pmu); in perf_pmus__destroy()
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| H A D | pmu.c | 20 #include "pmu.h"
22 #include <util/pmu-bison.h>
23 #include <util/pmu-flex.h>
40 /* An event loaded from /sys/devices/<pmu>/events. */
45 * An event loaded from a /sys/devices/<pmu>/identifier matched json
53 * pmu-events.c, created by parsing the pmu-events json files.
73 * differ from the PMU name as it won't have suffixes.
128 static int pmu_aliases_parse(struct perf_pmu *pmu);
171 static void perf_pmu_format__load(struct perf_pmu *pmu, struct perf_pmu_format *format) in perf_pmu_format__load() argument
179 if (!perf_pmu__pathname_scnprintf(path, sizeof(path), pmu->name, "format")) in perf_pmu_format__load()
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| H A D | pmu.h | 12 #include "pmu-events/pmu-events.h"
41 /** @name: The name of the PMU such as "cpu". */
44 * @alias_name: Optional alternate name for the PMU determined in
49 * @id: Optional PMU identifier read from
59 * @selectable: Can the PMU name be selected as if it were an event?
63 * @is_core: Is the PMU the core CPU PMU? Determined by the name being
66 * PMU on systems like Intel hybrid.
70 * @is_uncore: Is the PMU not within the CPU core? Determined by the
80 * @formats_checked: Only check PMU's formats are valid for
90 * PMU, read from
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
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| /openbmc/linux/Documentation/devicetree/bindings/soc/samsung/ |
| H A D | exynos-pmu.yaml | 4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
7 title: Samsung Exynos SoC series Power Management Unit (PMU)
18 - samsung,exynos3250-pmu
19 - samsung,exynos4210-pmu
20 - samsung,exynos4212-pmu
21 - samsung,exynos4412-pmu
22 - samsung,exynos5250-pmu
23 - samsung,exynos5260-pmu
24 - samsung,exynos5410-pmu
25 - samsung,exynos5420-pmu
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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_pmu.c | 142 static bool pmu_needs_timer(struct i915_pmu *pmu) in pmu_needs_timer() argument
144 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu); in pmu_needs_timer()
152 enable = pmu->enable; in pmu_needs_timer()
194 static u64 read_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample) in read_sample() argument
196 return pmu->sample[gt_id][sample].cur; in read_sample()
200 store_sample(struct i915_pmu *pmu, unsigned int gt_id, int sample, u64 val) in store_sample() argument
202 pmu->sample[gt_id][sample].cur = val; in store_sample()
206 add_sample_mult(struct i915_pmu *pmu, unsigned int gt_id, int sample, u32 val, u32 mul) in add_sample_mult() argument
208 pmu->sample[gt_id][sample].cur += mul_u32_u32(val, mul); in add_sample_mult()
215 struct i915_pmu *pmu = &i915->pmu; in get_rc6() local
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| /openbmc/linux/drivers/perf/ |
| H A D | fsl_imx8_ddr_perf.c | 43 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
56 const char *identifier; /* system PMU identifier for userspace */
86 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
87 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
88 { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
89 { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
90 { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
91 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
97 struct pmu pmu; member
114 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
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| H A D | fsl_imx9_ddr_perf.c | 45 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
53 const char *identifier; /* system PMU identifier for userspace */
57 struct pmu pmu; member
75 {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data},
84 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_identifier_show() local
86 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
104 struct ddr_pmu *pmu = dev_get_drvdata(dev); in ddr_perf_cpumask_show() local
106 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
271 static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter) in ddr_perf_clear_counter() argument
274 writel(0, pmu->base + PMC(counter) + 0x4); in ddr_perf_clear_counter()
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| H A D | marvell_cn10k_ddr_pmu.c | 125 struct pmu pmu; member
135 #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
233 struct cn10k_ddr_pmu *pmu = dev_get_drvdata(dev); in cn10k_ddr_perf_cpumask_show() local
235 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in cn10k_ddr_perf_cpumask_show()
289 static int cn10k_ddr_perf_alloc_counter(struct cn10k_ddr_pmu *pmu, in cn10k_ddr_perf_alloc_counter() argument
297 pmu->events[DDRC_PERF_READ_COUNTER_IDX] = event; in cn10k_ddr_perf_alloc_counter()
303 pmu->events[DDRC_PERF_WRITE_COUNTER_IDX] = event; in cn10k_ddr_perf_alloc_counter()
309 if (pmu->events[i] == NULL) { in cn10k_ddr_perf_alloc_counter()
310 pmu->events[i] = event; in cn10k_ddr_perf_alloc_counter()
318 static void cn10k_ddr_perf_free_counter(struct cn10k_ddr_pmu *pmu, int counter) in cn10k_ddr_perf_free_counter() argument
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| H A D | arm_pmu_platform.c | 25 static int probe_current_pmu(struct arm_pmu *pmu, in probe_current_pmu() argument
32 pr_info("probing PMU on CPU %d\n", cpu); in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
45 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq) in pmu_parse_percpu_irq() argument
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
95 static int pmu_parse_irqs(struct arm_pmu *pmu) in pmu_parse_irqs() argument
98 struct platform_device *pdev = pmu->plat_device; in pmu_parse_irqs()
99 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_irqs()
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| H A D | Kconfig | 10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
53 bool "ARM PMU framework"
61 bool "RISC-V PMU framework"
65 systems. This provides the core PMU framework that abstracts common
66 PMU functionalities in a core library so that different PMU drivers
71 bool "RISC-V legacy PMU implementation"
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| H A D | arm_pmu.c | 185 if (type == event->pmu->type) in armpmu_map_event()
202 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_set_period()
244 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_event_update()
274 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_stop()
278 * ARM pmu always has to update the counter, so ignore in armpmu_stop()
290 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_start()
294 * ARM pmu always has to reprogram the period, so ignore in armpmu_start()
315 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_del()
331 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); in armpmu_add()
364 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, in validate_event() argument
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| /openbmc/linux/drivers/soc/dove/ |
| H A D | pmu.c | 3 * Marvell Dove PMU support
17 #include <linux/soc/dove/pmu.h>
42 * The PMU contains a register to reset various subsystems within the
50 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_reset() local
54 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_reset()
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
57 writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
58 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_reset()
65 struct pmu_data *pmu = rcdev_to_pmu(rc); in pmu_reset_assert() local
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| /openbmc/linux/arch/x86/kvm/svm/ |
| H A D | pmu.c | 3 * KVM PMU support for AMD
20 #include "pmu.h"
28 static struct kvm_pmc *amd_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) in amd_pmc_idx_to_pmc() argument
30 unsigned int num_counters = pmu->nr_arch_gp_counters; in amd_pmc_idx_to_pmc()
35 return &pmu->gp_counters[array_index_nospec(pmc_idx, num_counters)]; in amd_pmc_idx_to_pmc()
38 static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr, in get_gp_pmc_amd() argument
41 struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu); in get_gp_pmc_amd()
52 * Each PMU counter has a pair of CTL and CTR MSRs. CTLn in get_gp_pmc_amd()
73 return amd_pmc_idx_to_pmc(pmu, idx); in get_gp_pmc_amd()
83 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); in amd_is_valid_rdpmc_ecx() local
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| /openbmc/linux/drivers/pmdomain/starfive/ |
| H A D | jh71xx-pmu.c | 3 * StarFive JH71XX PMU (Power Management Unit) Controller Driver
16 #include <dt-bindings/power/starfive,jh7110-pmu.h>
34 /* pmu int status */
66 spinlock_t lock; /* protects pmu reg */
71 struct jh71xx_pmu *pmu; member
77 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_get_state() local
82 *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; in jh71xx_pmu_get_state()
89 struct jh71xx_pmu *pmu = pmd->pmu; in jh71xx_pmu_set_state() local
100 dev_dbg(pmu->dev, "unable to get current state for %s\n", in jh71xx_pmu_set_state()
106 dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", in jh71xx_pmu_set_state()
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| /openbmc/linux/drivers/perf/amlogic/ |
| H A D | meson_ddr_pmu_core.c | 21 struct pmu pmu; member
35 #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
38 static void dmc_pmu_enable(struct ddr_pmu *pmu) in dmc_pmu_enable() argument
40 if (!pmu->pmu_enabled) in dmc_pmu_enable()
41 pmu->info.hw_info->enable(&pmu->info); in dmc_pmu_enable()
43 pmu->pmu_enabled = true; in dmc_pmu_enable()
46 static void dmc_pmu_disable(struct ddr_pmu *pmu) in dmc_pmu_disable() argument
48 if (pmu->pmu_enabled) in dmc_pmu_disable()
49 pmu->info.hw_info->disable(&pmu->info); in dmc_pmu_disable()
51 pmu->pmu_enabled = false; in dmc_pmu_disable()
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| /openbmc/linux/arch/x86/kvm/vmx/ |
| H A D | pmu_intel.c | 3 * KVM PMU support for Intel CPUs
21 #include "pmu.h"
71 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data) in reprogram_fixed_counters() argument
74 u64 old_fixed_ctr_ctrl = pmu->fixed_ctr_ctrl; in reprogram_fixed_counters()
77 pmu->fixed_ctr_ctrl = data; in reprogram_fixed_counters()
78 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { in reprogram_fixed_counters()
85 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i); in reprogram_fixed_counters()
87 __set_bit(INTEL_PMC_IDX_FIXED + i, pmu->pmc_in_use); in reprogram_fixed_counters()
92 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) in intel_pmc_idx_to_pmc() argument
95 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, in intel_pmc_idx_to_pmc()
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| /openbmc/linux/Documentation/devicetree/bindings/arm/rockchip/ |
| H A D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
7 title: Rockchip Power Management Unit (PMU)
14 The PMU is used to turn on and off different power domains of the SoCs.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
24 - rockchip,rk3128-pmu
25 - rockchip,rk3288-pmu
26 - rockchip,rk3368-pmu
27 - rockchip,rk3399-pmu
28 - rockchip,rk3568-pmu
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | marvell,dove-pinctrl.txt | 9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
14 Note: pmu* also allows for Power Management functions listed below
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
21 uart1(rts), pmu*
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
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| /openbmc/linux/Documentation/devicetree/bindings/perf/ |
| H A D | apm-xgene-pmu.txt | 1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
4 The following PMU devices are supported:
11 The following section describes the SoC PMU DT node binding.
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
19 - reg : First resource shall be the CPU bus PMU resource.
20 - interrupts : Interrupt-specifier for PMU IRQ.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
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| /openbmc/linux/tools/perf/tests/ |
| H A D | pmu-events.c | 4 #include "pmu.h"
12 #include "../pmu-events/pmu-events.h"
22 /* used for matching against events from generated pmu-events.c */
36 /* PMU which we should match against */
41 struct perf_pmu pmu; member
47 .pmu = "default_core",
59 .pmu = "default_core",
71 .pmu = "default_core",
83 .pmu = "default_core",
95 .pmu = "default_core",
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