1*e2ad626fSUlf Hansson // SPDX-License-Identifier: GPL-2.0-or-later
2*e2ad626fSUlf Hansson /*
3*e2ad626fSUlf Hansson * StarFive JH71XX PMU (Power Management Unit) Controller Driver
4*e2ad626fSUlf Hansson *
5*e2ad626fSUlf Hansson * Copyright (C) 2022 StarFive Technology Co., Ltd.
6*e2ad626fSUlf Hansson */
7*e2ad626fSUlf Hansson
8*e2ad626fSUlf Hansson #include <linux/interrupt.h>
9*e2ad626fSUlf Hansson #include <linux/io.h>
10*e2ad626fSUlf Hansson #include <linux/iopoll.h>
11*e2ad626fSUlf Hansson #include <linux/module.h>
12*e2ad626fSUlf Hansson #include <linux/of.h>
13*e2ad626fSUlf Hansson #include <linux/of_device.h>
14*e2ad626fSUlf Hansson #include <linux/platform_device.h>
15*e2ad626fSUlf Hansson #include <linux/pm_domain.h>
16*e2ad626fSUlf Hansson #include <dt-bindings/power/starfive,jh7110-pmu.h>
17*e2ad626fSUlf Hansson
18*e2ad626fSUlf Hansson /* register offset */
19*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_TURN_ON_POWER 0x0C
20*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_TURN_OFF_POWER 0x10
21*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_ENCOURAGE 0x44
22*e2ad626fSUlf Hansson #define JH71XX_PMU_TIMER_INT_MASK 0x48
23*e2ad626fSUlf Hansson #define JH71XX_PMU_CURR_POWER_MODE 0x80
24*e2ad626fSUlf Hansson #define JH71XX_PMU_EVENT_STATUS 0x88
25*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_STATUS 0x8C
26*e2ad626fSUlf Hansson
27*e2ad626fSUlf Hansson /* sw encourage cfg */
28*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05
29*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50
30*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_ENCOURAGE_DIS_LO 0x0A
31*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_ENCOURAGE_DIS_HI 0xA0
32*e2ad626fSUlf Hansson #define JH71XX_PMU_SW_ENCOURAGE_ON 0xFF
33*e2ad626fSUlf Hansson
34*e2ad626fSUlf Hansson /* pmu int status */
35*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_SEQ_DONE BIT(0)
36*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_HW_REQ BIT(1)
37*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_SW_FAIL GENMASK(3, 2)
38*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_HW_FAIL GENMASK(5, 4)
39*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_PCH_FAIL GENMASK(8, 6)
40*e2ad626fSUlf Hansson #define JH71XX_PMU_INT_ALL_MASK GENMASK(8, 0)
41*e2ad626fSUlf Hansson
42*e2ad626fSUlf Hansson /*
43*e2ad626fSUlf Hansson * The time required for switching power status is based on the time
44*e2ad626fSUlf Hansson * to turn on the largest domain's power, which is at microsecond level
45*e2ad626fSUlf Hansson */
46*e2ad626fSUlf Hansson #define JH71XX_PMU_TIMEOUT_US 100
47*e2ad626fSUlf Hansson
48*e2ad626fSUlf Hansson struct jh71xx_domain_info {
49*e2ad626fSUlf Hansson const char * const name;
50*e2ad626fSUlf Hansson unsigned int flags;
51*e2ad626fSUlf Hansson u8 bit;
52*e2ad626fSUlf Hansson };
53*e2ad626fSUlf Hansson
54*e2ad626fSUlf Hansson struct jh71xx_pmu_match_data {
55*e2ad626fSUlf Hansson const struct jh71xx_domain_info *domain_info;
56*e2ad626fSUlf Hansson int num_domains;
57*e2ad626fSUlf Hansson };
58*e2ad626fSUlf Hansson
59*e2ad626fSUlf Hansson struct jh71xx_pmu {
60*e2ad626fSUlf Hansson struct device *dev;
61*e2ad626fSUlf Hansson const struct jh71xx_pmu_match_data *match_data;
62*e2ad626fSUlf Hansson void __iomem *base;
63*e2ad626fSUlf Hansson struct generic_pm_domain **genpd;
64*e2ad626fSUlf Hansson struct genpd_onecell_data genpd_data;
65*e2ad626fSUlf Hansson int irq;
66*e2ad626fSUlf Hansson spinlock_t lock; /* protects pmu reg */
67*e2ad626fSUlf Hansson };
68*e2ad626fSUlf Hansson
69*e2ad626fSUlf Hansson struct jh71xx_pmu_dev {
70*e2ad626fSUlf Hansson const struct jh71xx_domain_info *domain_info;
71*e2ad626fSUlf Hansson struct jh71xx_pmu *pmu;
72*e2ad626fSUlf Hansson struct generic_pm_domain genpd;
73*e2ad626fSUlf Hansson };
74*e2ad626fSUlf Hansson
jh71xx_pmu_get_state(struct jh71xx_pmu_dev * pmd,u32 mask,bool * is_on)75*e2ad626fSUlf Hansson static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
76*e2ad626fSUlf Hansson {
77*e2ad626fSUlf Hansson struct jh71xx_pmu *pmu = pmd->pmu;
78*e2ad626fSUlf Hansson
79*e2ad626fSUlf Hansson if (!mask)
80*e2ad626fSUlf Hansson return -EINVAL;
81*e2ad626fSUlf Hansson
82*e2ad626fSUlf Hansson *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask;
83*e2ad626fSUlf Hansson
84*e2ad626fSUlf Hansson return 0;
85*e2ad626fSUlf Hansson }
86*e2ad626fSUlf Hansson
jh71xx_pmu_set_state(struct jh71xx_pmu_dev * pmd,u32 mask,bool on)87*e2ad626fSUlf Hansson static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on)
88*e2ad626fSUlf Hansson {
89*e2ad626fSUlf Hansson struct jh71xx_pmu *pmu = pmd->pmu;
90*e2ad626fSUlf Hansson unsigned long flags;
91*e2ad626fSUlf Hansson u32 val;
92*e2ad626fSUlf Hansson u32 mode;
93*e2ad626fSUlf Hansson u32 encourage_lo;
94*e2ad626fSUlf Hansson u32 encourage_hi;
95*e2ad626fSUlf Hansson bool is_on;
96*e2ad626fSUlf Hansson int ret;
97*e2ad626fSUlf Hansson
98*e2ad626fSUlf Hansson ret = jh71xx_pmu_get_state(pmd, mask, &is_on);
99*e2ad626fSUlf Hansson if (ret) {
100*e2ad626fSUlf Hansson dev_dbg(pmu->dev, "unable to get current state for %s\n",
101*e2ad626fSUlf Hansson pmd->genpd.name);
102*e2ad626fSUlf Hansson return ret;
103*e2ad626fSUlf Hansson }
104*e2ad626fSUlf Hansson
105*e2ad626fSUlf Hansson if (is_on == on) {
106*e2ad626fSUlf Hansson dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n",
107*e2ad626fSUlf Hansson pmd->genpd.name, on ? "en" : "dis");
108*e2ad626fSUlf Hansson return 0;
109*e2ad626fSUlf Hansson }
110*e2ad626fSUlf Hansson
111*e2ad626fSUlf Hansson spin_lock_irqsave(&pmu->lock, flags);
112*e2ad626fSUlf Hansson
113*e2ad626fSUlf Hansson /*
114*e2ad626fSUlf Hansson * The PMU accepts software encourage to switch power mode in the following 2 steps:
115*e2ad626fSUlf Hansson *
116*e2ad626fSUlf Hansson * 1.Configure the register SW_TURN_ON_POWER (offset 0x0c) by writing 1 to
117*e2ad626fSUlf Hansson * the bit corresponding to the power domain that will be turned on
118*e2ad626fSUlf Hansson * and writing 0 to the others.
119*e2ad626fSUlf Hansson * Likewise, configure the register SW_TURN_OFF_POWER (offset 0x10) by
120*e2ad626fSUlf Hansson * writing 1 to the bit corresponding to the power domain that will be
121*e2ad626fSUlf Hansson * turned off and writing 0 to the others.
122*e2ad626fSUlf Hansson */
123*e2ad626fSUlf Hansson if (on) {
124*e2ad626fSUlf Hansson mode = JH71XX_PMU_SW_TURN_ON_POWER;
125*e2ad626fSUlf Hansson encourage_lo = JH71XX_PMU_SW_ENCOURAGE_EN_LO;
126*e2ad626fSUlf Hansson encourage_hi = JH71XX_PMU_SW_ENCOURAGE_EN_HI;
127*e2ad626fSUlf Hansson } else {
128*e2ad626fSUlf Hansson mode = JH71XX_PMU_SW_TURN_OFF_POWER;
129*e2ad626fSUlf Hansson encourage_lo = JH71XX_PMU_SW_ENCOURAGE_DIS_LO;
130*e2ad626fSUlf Hansson encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI;
131*e2ad626fSUlf Hansson }
132*e2ad626fSUlf Hansson
133*e2ad626fSUlf Hansson writel(mask, pmu->base + mode);
134*e2ad626fSUlf Hansson
135*e2ad626fSUlf Hansson /*
136*e2ad626fSUlf Hansson * 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44)
137*e2ad626fSUlf Hansson * First write SW_MODE_ENCOURAGE_ON to JH71XX_PMU_SW_ENCOURAGE. This will reset
138*e2ad626fSUlf Hansson * the state machine which parses the command sequence. This register must be
139*e2ad626fSUlf Hansson * written every time software wants to power on/off a domain.
140*e2ad626fSUlf Hansson * Then write the lower bits of the command sequence, followed by the upper
141*e2ad626fSUlf Hansson * bits. The sequence differs between powering on & off a domain.
142*e2ad626fSUlf Hansson */
143*e2ad626fSUlf Hansson writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
144*e2ad626fSUlf Hansson writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
145*e2ad626fSUlf Hansson writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE);
146*e2ad626fSUlf Hansson
147*e2ad626fSUlf Hansson spin_unlock_irqrestore(&pmu->lock, flags);
148*e2ad626fSUlf Hansson
149*e2ad626fSUlf Hansson /* Wait for the power domain bit to be enabled / disabled */
150*e2ad626fSUlf Hansson if (on) {
151*e2ad626fSUlf Hansson ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
152*e2ad626fSUlf Hansson val, val & mask,
153*e2ad626fSUlf Hansson 1, JH71XX_PMU_TIMEOUT_US);
154*e2ad626fSUlf Hansson } else {
155*e2ad626fSUlf Hansson ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE,
156*e2ad626fSUlf Hansson val, !(val & mask),
157*e2ad626fSUlf Hansson 1, JH71XX_PMU_TIMEOUT_US);
158*e2ad626fSUlf Hansson }
159*e2ad626fSUlf Hansson
160*e2ad626fSUlf Hansson if (ret) {
161*e2ad626fSUlf Hansson dev_err(pmu->dev, "%s: failed to power %s\n",
162*e2ad626fSUlf Hansson pmd->genpd.name, on ? "on" : "off");
163*e2ad626fSUlf Hansson return -ETIMEDOUT;
164*e2ad626fSUlf Hansson }
165*e2ad626fSUlf Hansson
166*e2ad626fSUlf Hansson return 0;
167*e2ad626fSUlf Hansson }
168*e2ad626fSUlf Hansson
jh71xx_pmu_on(struct generic_pm_domain * genpd)169*e2ad626fSUlf Hansson static int jh71xx_pmu_on(struct generic_pm_domain *genpd)
170*e2ad626fSUlf Hansson {
171*e2ad626fSUlf Hansson struct jh71xx_pmu_dev *pmd = container_of(genpd,
172*e2ad626fSUlf Hansson struct jh71xx_pmu_dev, genpd);
173*e2ad626fSUlf Hansson u32 pwr_mask = BIT(pmd->domain_info->bit);
174*e2ad626fSUlf Hansson
175*e2ad626fSUlf Hansson return jh71xx_pmu_set_state(pmd, pwr_mask, true);
176*e2ad626fSUlf Hansson }
177*e2ad626fSUlf Hansson
jh71xx_pmu_off(struct generic_pm_domain * genpd)178*e2ad626fSUlf Hansson static int jh71xx_pmu_off(struct generic_pm_domain *genpd)
179*e2ad626fSUlf Hansson {
180*e2ad626fSUlf Hansson struct jh71xx_pmu_dev *pmd = container_of(genpd,
181*e2ad626fSUlf Hansson struct jh71xx_pmu_dev, genpd);
182*e2ad626fSUlf Hansson u32 pwr_mask = BIT(pmd->domain_info->bit);
183*e2ad626fSUlf Hansson
184*e2ad626fSUlf Hansson return jh71xx_pmu_set_state(pmd, pwr_mask, false);
185*e2ad626fSUlf Hansson }
186*e2ad626fSUlf Hansson
jh71xx_pmu_int_enable(struct jh71xx_pmu * pmu,u32 mask,bool enable)187*e2ad626fSUlf Hansson static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable)
188*e2ad626fSUlf Hansson {
189*e2ad626fSUlf Hansson u32 val;
190*e2ad626fSUlf Hansson unsigned long flags;
191*e2ad626fSUlf Hansson
192*e2ad626fSUlf Hansson spin_lock_irqsave(&pmu->lock, flags);
193*e2ad626fSUlf Hansson val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK);
194*e2ad626fSUlf Hansson
195*e2ad626fSUlf Hansson if (enable)
196*e2ad626fSUlf Hansson val &= ~mask;
197*e2ad626fSUlf Hansson else
198*e2ad626fSUlf Hansson val |= mask;
199*e2ad626fSUlf Hansson
200*e2ad626fSUlf Hansson writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK);
201*e2ad626fSUlf Hansson spin_unlock_irqrestore(&pmu->lock, flags);
202*e2ad626fSUlf Hansson }
203*e2ad626fSUlf Hansson
jh71xx_pmu_interrupt(int irq,void * data)204*e2ad626fSUlf Hansson static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data)
205*e2ad626fSUlf Hansson {
206*e2ad626fSUlf Hansson struct jh71xx_pmu *pmu = data;
207*e2ad626fSUlf Hansson u32 val;
208*e2ad626fSUlf Hansson
209*e2ad626fSUlf Hansson val = readl(pmu->base + JH71XX_PMU_INT_STATUS);
210*e2ad626fSUlf Hansson
211*e2ad626fSUlf Hansson if (val & JH71XX_PMU_INT_SEQ_DONE)
212*e2ad626fSUlf Hansson dev_dbg(pmu->dev, "sequence done.\n");
213*e2ad626fSUlf Hansson if (val & JH71XX_PMU_INT_HW_REQ)
214*e2ad626fSUlf Hansson dev_dbg(pmu->dev, "hardware encourage requestion.\n");
215*e2ad626fSUlf Hansson if (val & JH71XX_PMU_INT_SW_FAIL)
216*e2ad626fSUlf Hansson dev_err(pmu->dev, "software encourage fail.\n");
217*e2ad626fSUlf Hansson if (val & JH71XX_PMU_INT_HW_FAIL)
218*e2ad626fSUlf Hansson dev_err(pmu->dev, "hardware encourage fail.\n");
219*e2ad626fSUlf Hansson if (val & JH71XX_PMU_INT_PCH_FAIL)
220*e2ad626fSUlf Hansson dev_err(pmu->dev, "p-channel fail event.\n");
221*e2ad626fSUlf Hansson
222*e2ad626fSUlf Hansson /* clear interrupts */
223*e2ad626fSUlf Hansson writel(val, pmu->base + JH71XX_PMU_INT_STATUS);
224*e2ad626fSUlf Hansson writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS);
225*e2ad626fSUlf Hansson
226*e2ad626fSUlf Hansson return IRQ_HANDLED;
227*e2ad626fSUlf Hansson }
228*e2ad626fSUlf Hansson
jh71xx_pmu_init_domain(struct jh71xx_pmu * pmu,int index)229*e2ad626fSUlf Hansson static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index)
230*e2ad626fSUlf Hansson {
231*e2ad626fSUlf Hansson struct jh71xx_pmu_dev *pmd;
232*e2ad626fSUlf Hansson u32 pwr_mask;
233*e2ad626fSUlf Hansson int ret;
234*e2ad626fSUlf Hansson bool is_on = false;
235*e2ad626fSUlf Hansson
236*e2ad626fSUlf Hansson pmd = devm_kzalloc(pmu->dev, sizeof(*pmd), GFP_KERNEL);
237*e2ad626fSUlf Hansson if (!pmd)
238*e2ad626fSUlf Hansson return -ENOMEM;
239*e2ad626fSUlf Hansson
240*e2ad626fSUlf Hansson pmd->domain_info = &pmu->match_data->domain_info[index];
241*e2ad626fSUlf Hansson pmd->pmu = pmu;
242*e2ad626fSUlf Hansson pwr_mask = BIT(pmd->domain_info->bit);
243*e2ad626fSUlf Hansson
244*e2ad626fSUlf Hansson pmd->genpd.name = pmd->domain_info->name;
245*e2ad626fSUlf Hansson pmd->genpd.flags = pmd->domain_info->flags;
246*e2ad626fSUlf Hansson
247*e2ad626fSUlf Hansson ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on);
248*e2ad626fSUlf Hansson if (ret)
249*e2ad626fSUlf Hansson dev_warn(pmu->dev, "unable to get current state for %s\n",
250*e2ad626fSUlf Hansson pmd->genpd.name);
251*e2ad626fSUlf Hansson
252*e2ad626fSUlf Hansson pmd->genpd.power_on = jh71xx_pmu_on;
253*e2ad626fSUlf Hansson pmd->genpd.power_off = jh71xx_pmu_off;
254*e2ad626fSUlf Hansson pm_genpd_init(&pmd->genpd, NULL, !is_on);
255*e2ad626fSUlf Hansson
256*e2ad626fSUlf Hansson pmu->genpd_data.domains[index] = &pmd->genpd;
257*e2ad626fSUlf Hansson
258*e2ad626fSUlf Hansson return 0;
259*e2ad626fSUlf Hansson }
260*e2ad626fSUlf Hansson
jh71xx_pmu_probe(struct platform_device * pdev)261*e2ad626fSUlf Hansson static int jh71xx_pmu_probe(struct platform_device *pdev)
262*e2ad626fSUlf Hansson {
263*e2ad626fSUlf Hansson struct device *dev = &pdev->dev;
264*e2ad626fSUlf Hansson struct device_node *np = dev->of_node;
265*e2ad626fSUlf Hansson const struct jh71xx_pmu_match_data *match_data;
266*e2ad626fSUlf Hansson struct jh71xx_pmu *pmu;
267*e2ad626fSUlf Hansson unsigned int i;
268*e2ad626fSUlf Hansson int ret;
269*e2ad626fSUlf Hansson
270*e2ad626fSUlf Hansson pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
271*e2ad626fSUlf Hansson if (!pmu)
272*e2ad626fSUlf Hansson return -ENOMEM;
273*e2ad626fSUlf Hansson
274*e2ad626fSUlf Hansson pmu->base = devm_platform_ioremap_resource(pdev, 0);
275*e2ad626fSUlf Hansson if (IS_ERR(pmu->base))
276*e2ad626fSUlf Hansson return PTR_ERR(pmu->base);
277*e2ad626fSUlf Hansson
278*e2ad626fSUlf Hansson pmu->irq = platform_get_irq(pdev, 0);
279*e2ad626fSUlf Hansson if (pmu->irq < 0)
280*e2ad626fSUlf Hansson return pmu->irq;
281*e2ad626fSUlf Hansson
282*e2ad626fSUlf Hansson ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt,
283*e2ad626fSUlf Hansson 0, pdev->name, pmu);
284*e2ad626fSUlf Hansson if (ret)
285*e2ad626fSUlf Hansson dev_err(dev, "failed to request irq\n");
286*e2ad626fSUlf Hansson
287*e2ad626fSUlf Hansson match_data = of_device_get_match_data(dev);
288*e2ad626fSUlf Hansson if (!match_data)
289*e2ad626fSUlf Hansson return -EINVAL;
290*e2ad626fSUlf Hansson
291*e2ad626fSUlf Hansson pmu->genpd = devm_kcalloc(dev, match_data->num_domains,
292*e2ad626fSUlf Hansson sizeof(struct generic_pm_domain *),
293*e2ad626fSUlf Hansson GFP_KERNEL);
294*e2ad626fSUlf Hansson if (!pmu->genpd)
295*e2ad626fSUlf Hansson return -ENOMEM;
296*e2ad626fSUlf Hansson
297*e2ad626fSUlf Hansson pmu->dev = dev;
298*e2ad626fSUlf Hansson pmu->match_data = match_data;
299*e2ad626fSUlf Hansson pmu->genpd_data.domains = pmu->genpd;
300*e2ad626fSUlf Hansson pmu->genpd_data.num_domains = match_data->num_domains;
301*e2ad626fSUlf Hansson
302*e2ad626fSUlf Hansson for (i = 0; i < match_data->num_domains; i++) {
303*e2ad626fSUlf Hansson ret = jh71xx_pmu_init_domain(pmu, i);
304*e2ad626fSUlf Hansson if (ret) {
305*e2ad626fSUlf Hansson dev_err(dev, "failed to initialize power domain\n");
306*e2ad626fSUlf Hansson return ret;
307*e2ad626fSUlf Hansson }
308*e2ad626fSUlf Hansson }
309*e2ad626fSUlf Hansson
310*e2ad626fSUlf Hansson spin_lock_init(&pmu->lock);
311*e2ad626fSUlf Hansson jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true);
312*e2ad626fSUlf Hansson
313*e2ad626fSUlf Hansson ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
314*e2ad626fSUlf Hansson if (ret) {
315*e2ad626fSUlf Hansson dev_err(dev, "failed to register genpd driver: %d\n", ret);
316*e2ad626fSUlf Hansson return ret;
317*e2ad626fSUlf Hansson }
318*e2ad626fSUlf Hansson
319*e2ad626fSUlf Hansson dev_dbg(dev, "registered %u power domains\n", i);
320*e2ad626fSUlf Hansson
321*e2ad626fSUlf Hansson return 0;
322*e2ad626fSUlf Hansson }
323*e2ad626fSUlf Hansson
324*e2ad626fSUlf Hansson static const struct jh71xx_domain_info jh7110_power_domains[] = {
325*e2ad626fSUlf Hansson [JH7110_PD_SYSTOP] = {
326*e2ad626fSUlf Hansson .name = "SYSTOP",
327*e2ad626fSUlf Hansson .bit = 0,
328*e2ad626fSUlf Hansson .flags = GENPD_FLAG_ALWAYS_ON,
329*e2ad626fSUlf Hansson },
330*e2ad626fSUlf Hansson [JH7110_PD_CPU] = {
331*e2ad626fSUlf Hansson .name = "CPU",
332*e2ad626fSUlf Hansson .bit = 1,
333*e2ad626fSUlf Hansson .flags = GENPD_FLAG_ALWAYS_ON,
334*e2ad626fSUlf Hansson },
335*e2ad626fSUlf Hansson [JH7110_PD_GPUA] = {
336*e2ad626fSUlf Hansson .name = "GPUA",
337*e2ad626fSUlf Hansson .bit = 2,
338*e2ad626fSUlf Hansson },
339*e2ad626fSUlf Hansson [JH7110_PD_VDEC] = {
340*e2ad626fSUlf Hansson .name = "VDEC",
341*e2ad626fSUlf Hansson .bit = 3,
342*e2ad626fSUlf Hansson },
343*e2ad626fSUlf Hansson [JH7110_PD_VOUT] = {
344*e2ad626fSUlf Hansson .name = "VOUT",
345*e2ad626fSUlf Hansson .bit = 4,
346*e2ad626fSUlf Hansson },
347*e2ad626fSUlf Hansson [JH7110_PD_ISP] = {
348*e2ad626fSUlf Hansson .name = "ISP",
349*e2ad626fSUlf Hansson .bit = 5,
350*e2ad626fSUlf Hansson },
351*e2ad626fSUlf Hansson [JH7110_PD_VENC] = {
352*e2ad626fSUlf Hansson .name = "VENC",
353*e2ad626fSUlf Hansson .bit = 6,
354*e2ad626fSUlf Hansson },
355*e2ad626fSUlf Hansson };
356*e2ad626fSUlf Hansson
357*e2ad626fSUlf Hansson static const struct jh71xx_pmu_match_data jh7110_pmu = {
358*e2ad626fSUlf Hansson .num_domains = ARRAY_SIZE(jh7110_power_domains),
359*e2ad626fSUlf Hansson .domain_info = jh7110_power_domains,
360*e2ad626fSUlf Hansson };
361*e2ad626fSUlf Hansson
362*e2ad626fSUlf Hansson static const struct of_device_id jh71xx_pmu_of_match[] = {
363*e2ad626fSUlf Hansson {
364*e2ad626fSUlf Hansson .compatible = "starfive,jh7110-pmu",
365*e2ad626fSUlf Hansson .data = (void *)&jh7110_pmu,
366*e2ad626fSUlf Hansson }, {
367*e2ad626fSUlf Hansson /* sentinel */
368*e2ad626fSUlf Hansson }
369*e2ad626fSUlf Hansson };
370*e2ad626fSUlf Hansson
371*e2ad626fSUlf Hansson static struct platform_driver jh71xx_pmu_driver = {
372*e2ad626fSUlf Hansson .probe = jh71xx_pmu_probe,
373*e2ad626fSUlf Hansson .driver = {
374*e2ad626fSUlf Hansson .name = "jh71xx-pmu",
375*e2ad626fSUlf Hansson .of_match_table = jh71xx_pmu_of_match,
376*e2ad626fSUlf Hansson .suppress_bind_attrs = true,
377*e2ad626fSUlf Hansson },
378*e2ad626fSUlf Hansson };
379*e2ad626fSUlf Hansson builtin_platform_driver(jh71xx_pmu_driver);
380*e2ad626fSUlf Hansson
381*e2ad626fSUlf Hansson MODULE_AUTHOR("Walker Chen <walker.chen@starfivetech.com>");
382*e2ad626fSUlf Hansson MODULE_DESCRIPTION("StarFive JH71XX PMU Driver");
383*e2ad626fSUlf Hansson MODULE_LICENSE("GPL");
384