121b13791SBen Skeggs /*
221b13791SBen Skeggs * Copyright 2013 Red Hat Inc.
321b13791SBen Skeggs *
421b13791SBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining a
521b13791SBen Skeggs * copy of this software and associated documentation files (the "Software"),
621b13791SBen Skeggs * to deal in the Software without restriction, including without limitation
721b13791SBen Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
821b13791SBen Skeggs * and/or sell copies of the Software, and to permit persons to whom the
921b13791SBen Skeggs * Software is furnished to do so, subject to the following conditions:
1021b13791SBen Skeggs *
1121b13791SBen Skeggs * The above copyright notice and this permission notice shall be included in
1221b13791SBen Skeggs * all copies or substantial portions of the Software.
1321b13791SBen Skeggs *
1421b13791SBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1521b13791SBen Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1621b13791SBen Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1721b13791SBen Skeggs * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1821b13791SBen Skeggs * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1921b13791SBen Skeggs * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2021b13791SBen Skeggs * OTHER DEALINGS IN THE SOFTWARE.
2121b13791SBen Skeggs *
2221b13791SBen Skeggs * Authors: Ben Skeggs
2321b13791SBen Skeggs */
2421b13791SBen Skeggs #include "priv.h"
2521b13791SBen Skeggs #include "fuc/gt215.fuc3.h"
2621b13791SBen Skeggs
27da7d2062SBen Skeggs #include <subdev/timer.h>
28da7d2062SBen Skeggs
29da7d2062SBen Skeggs int
gt215_pmu_send(struct nvkm_pmu * pmu,u32 reply[2],u32 process,u32 message,u32 data0,u32 data1)30da7d2062SBen Skeggs gt215_pmu_send(struct nvkm_pmu *pmu, u32 reply[2],
31da7d2062SBen Skeggs u32 process, u32 message, u32 data0, u32 data1)
32da7d2062SBen Skeggs {
33da7d2062SBen Skeggs struct nvkm_subdev *subdev = &pmu->subdev;
34da7d2062SBen Skeggs struct nvkm_device *device = subdev->device;
35da7d2062SBen Skeggs u32 addr;
36da7d2062SBen Skeggs
375a479d45SBen Skeggs mutex_lock(&pmu->send.mutex);
38da7d2062SBen Skeggs /* wait for a free slot in the fifo */
39da7d2062SBen Skeggs addr = nvkm_rd32(device, 0x10a4a0);
40da7d2062SBen Skeggs if (nvkm_msec(device, 2000,
41da7d2062SBen Skeggs u32 tmp = nvkm_rd32(device, 0x10a4b0);
42da7d2062SBen Skeggs if (tmp != (addr ^ 8))
43da7d2062SBen Skeggs break;
44da7d2062SBen Skeggs ) < 0) {
455a479d45SBen Skeggs mutex_unlock(&pmu->send.mutex);
46da7d2062SBen Skeggs return -EBUSY;
47da7d2062SBen Skeggs }
48da7d2062SBen Skeggs
49da7d2062SBen Skeggs /* we currently only support a single process at a time waiting
50da7d2062SBen Skeggs * on a synchronous reply, take the PMU mutex and tell the
51da7d2062SBen Skeggs * receive handler what we're waiting for
52da7d2062SBen Skeggs */
53da7d2062SBen Skeggs if (reply) {
54da7d2062SBen Skeggs pmu->recv.message = message;
55da7d2062SBen Skeggs pmu->recv.process = process;
56da7d2062SBen Skeggs }
57da7d2062SBen Skeggs
58da7d2062SBen Skeggs /* acquire data segment access */
59da7d2062SBen Skeggs do {
60da7d2062SBen Skeggs nvkm_wr32(device, 0x10a580, 0x00000001);
61da7d2062SBen Skeggs } while (nvkm_rd32(device, 0x10a580) != 0x00000001);
62da7d2062SBen Skeggs
63da7d2062SBen Skeggs /* write the packet */
64da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
65da7d2062SBen Skeggs pmu->send.base));
66da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c4, process);
67da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c4, message);
68da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c4, data0);
69da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c4, data1);
70da7d2062SBen Skeggs nvkm_wr32(device, 0x10a4a0, (addr + 1) & 0x0f);
71da7d2062SBen Skeggs
72da7d2062SBen Skeggs /* release data segment access */
73da7d2062SBen Skeggs nvkm_wr32(device, 0x10a580, 0x00000000);
74da7d2062SBen Skeggs
75da7d2062SBen Skeggs /* wait for reply, if requested */
76da7d2062SBen Skeggs if (reply) {
77da7d2062SBen Skeggs wait_event(pmu->recv.wait, (pmu->recv.process == 0));
78da7d2062SBen Skeggs reply[0] = pmu->recv.data[0];
79da7d2062SBen Skeggs reply[1] = pmu->recv.data[1];
80da7d2062SBen Skeggs }
81da7d2062SBen Skeggs
825a479d45SBen Skeggs mutex_unlock(&pmu->send.mutex);
83da7d2062SBen Skeggs return 0;
84da7d2062SBen Skeggs }
85da7d2062SBen Skeggs
86da7d2062SBen Skeggs void
gt215_pmu_recv(struct nvkm_pmu * pmu)87da7d2062SBen Skeggs gt215_pmu_recv(struct nvkm_pmu *pmu)
88da7d2062SBen Skeggs {
89da7d2062SBen Skeggs struct nvkm_subdev *subdev = &pmu->subdev;
90da7d2062SBen Skeggs struct nvkm_device *device = subdev->device;
91da7d2062SBen Skeggs u32 process, message, data0, data1;
92da7d2062SBen Skeggs
93da7d2062SBen Skeggs /* nothing to do if GET == PUT */
94da7d2062SBen Skeggs u32 addr = nvkm_rd32(device, 0x10a4cc);
95da7d2062SBen Skeggs if (addr == nvkm_rd32(device, 0x10a4c8))
96da7d2062SBen Skeggs return;
97da7d2062SBen Skeggs
98da7d2062SBen Skeggs /* acquire data segment access */
99da7d2062SBen Skeggs do {
100da7d2062SBen Skeggs nvkm_wr32(device, 0x10a580, 0x00000002);
101da7d2062SBen Skeggs } while (nvkm_rd32(device, 0x10a580) != 0x00000002);
102da7d2062SBen Skeggs
103da7d2062SBen Skeggs /* read the packet */
104da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
105da7d2062SBen Skeggs pmu->recv.base));
106da7d2062SBen Skeggs process = nvkm_rd32(device, 0x10a1c4);
107da7d2062SBen Skeggs message = nvkm_rd32(device, 0x10a1c4);
108da7d2062SBen Skeggs data0 = nvkm_rd32(device, 0x10a1c4);
109da7d2062SBen Skeggs data1 = nvkm_rd32(device, 0x10a1c4);
110da7d2062SBen Skeggs nvkm_wr32(device, 0x10a4cc, (addr + 1) & 0x0f);
111da7d2062SBen Skeggs
112da7d2062SBen Skeggs /* release data segment access */
113da7d2062SBen Skeggs nvkm_wr32(device, 0x10a580, 0x00000000);
114da7d2062SBen Skeggs
115da7d2062SBen Skeggs /* wake process if it's waiting on a synchronous reply */
116da7d2062SBen Skeggs if (pmu->recv.process) {
117da7d2062SBen Skeggs if (process == pmu->recv.process &&
118da7d2062SBen Skeggs message == pmu->recv.message) {
119da7d2062SBen Skeggs pmu->recv.data[0] = data0;
120da7d2062SBen Skeggs pmu->recv.data[1] = data1;
121da7d2062SBen Skeggs pmu->recv.process = 0;
122da7d2062SBen Skeggs wake_up(&pmu->recv.wait);
123da7d2062SBen Skeggs return;
124da7d2062SBen Skeggs }
125da7d2062SBen Skeggs }
126da7d2062SBen Skeggs
127da7d2062SBen Skeggs /* right now there's no other expected responses from the engine,
128da7d2062SBen Skeggs * so assume that any unexpected message is an error.
129da7d2062SBen Skeggs */
130da7d2062SBen Skeggs nvkm_warn(subdev, "%c%c%c%c %08x %08x %08x %08x\n",
131da7d2062SBen Skeggs (char)((process & 0x000000ff) >> 0),
132da7d2062SBen Skeggs (char)((process & 0x0000ff00) >> 8),
133da7d2062SBen Skeggs (char)((process & 0x00ff0000) >> 16),
134da7d2062SBen Skeggs (char)((process & 0xff000000) >> 24),
135da7d2062SBen Skeggs process, message, data0, data1);
136da7d2062SBen Skeggs }
137da7d2062SBen Skeggs
138da7d2062SBen Skeggs void
gt215_pmu_intr(struct nvkm_pmu * pmu)139da7d2062SBen Skeggs gt215_pmu_intr(struct nvkm_pmu *pmu)
140da7d2062SBen Skeggs {
141da7d2062SBen Skeggs struct nvkm_subdev *subdev = &pmu->subdev;
142da7d2062SBen Skeggs struct nvkm_device *device = subdev->device;
143da7d2062SBen Skeggs u32 disp = nvkm_rd32(device, 0x10a01c);
144da7d2062SBen Skeggs u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16);
145da7d2062SBen Skeggs
146da7d2062SBen Skeggs if (intr & 0x00000020) {
147da7d2062SBen Skeggs u32 stat = nvkm_rd32(device, 0x10a16c);
148da7d2062SBen Skeggs if (stat & 0x80000000) {
149da7d2062SBen Skeggs nvkm_error(subdev, "UAS fault at %06x addr %08x\n",
150da7d2062SBen Skeggs stat & 0x00ffffff,
151da7d2062SBen Skeggs nvkm_rd32(device, 0x10a168));
152da7d2062SBen Skeggs nvkm_wr32(device, 0x10a16c, 0x00000000);
153da7d2062SBen Skeggs intr &= ~0x00000020;
154da7d2062SBen Skeggs }
155da7d2062SBen Skeggs }
156da7d2062SBen Skeggs
157da7d2062SBen Skeggs if (intr & 0x00000040) {
158da7d2062SBen Skeggs schedule_work(&pmu->recv.work);
159da7d2062SBen Skeggs nvkm_wr32(device, 0x10a004, 0x00000040);
160da7d2062SBen Skeggs intr &= ~0x00000040;
161da7d2062SBen Skeggs }
162da7d2062SBen Skeggs
163da7d2062SBen Skeggs if (intr & 0x00000080) {
164da7d2062SBen Skeggs nvkm_info(subdev, "wr32 %06x %08x\n",
165da7d2062SBen Skeggs nvkm_rd32(device, 0x10a7a0),
166da7d2062SBen Skeggs nvkm_rd32(device, 0x10a7a4));
167da7d2062SBen Skeggs nvkm_wr32(device, 0x10a004, 0x00000080);
168da7d2062SBen Skeggs intr &= ~0x00000080;
169da7d2062SBen Skeggs }
170da7d2062SBen Skeggs
171da7d2062SBen Skeggs if (intr) {
172da7d2062SBen Skeggs nvkm_error(subdev, "intr %08x\n", intr);
173da7d2062SBen Skeggs nvkm_wr32(device, 0x10a004, intr);
174da7d2062SBen Skeggs }
175da7d2062SBen Skeggs }
176da7d2062SBen Skeggs
177da7d2062SBen Skeggs void
gt215_pmu_fini(struct nvkm_pmu * pmu)178da7d2062SBen Skeggs gt215_pmu_fini(struct nvkm_pmu *pmu)
179da7d2062SBen Skeggs {
180da7d2062SBen Skeggs nvkm_wr32(pmu->subdev.device, 0x10a014, 0x00000060);
181*a9d90860SBen Skeggs flush_work(&pmu->recv.work);
182da7d2062SBen Skeggs }
183da7d2062SBen Skeggs
184715e7d26SBen Skeggs static void
gt215_pmu_reset(struct nvkm_pmu * pmu)185da7d2062SBen Skeggs gt215_pmu_reset(struct nvkm_pmu *pmu)
186da7d2062SBen Skeggs {
187da7d2062SBen Skeggs struct nvkm_device *device = pmu->subdev.device;
188ccdc0431SBen Skeggs
189715e7d26SBen Skeggs nvkm_mask(device, 0x022210, 0x00000001, 0x00000000);
190715e7d26SBen Skeggs nvkm_mask(device, 0x022210, 0x00000001, 0x00000001);
191715e7d26SBen Skeggs nvkm_rd32(device, 0x022210);
192da7d2062SBen Skeggs }
193da7d2062SBen Skeggs
1946b1277c8SBen Skeggs static bool
gt215_pmu_enabled(struct nvkm_pmu * pmu)1956b1277c8SBen Skeggs gt215_pmu_enabled(struct nvkm_pmu *pmu)
1966b1277c8SBen Skeggs {
1976b1277c8SBen Skeggs return nvkm_rd32(pmu->subdev.device, 0x022210) & 0x00000001;
1986b1277c8SBen Skeggs }
1996b1277c8SBen Skeggs
200da7d2062SBen Skeggs int
gt215_pmu_init(struct nvkm_pmu * pmu)201da7d2062SBen Skeggs gt215_pmu_init(struct nvkm_pmu *pmu)
202da7d2062SBen Skeggs {
203da7d2062SBen Skeggs struct nvkm_device *device = pmu->subdev.device;
204da7d2062SBen Skeggs int i;
205da7d2062SBen Skeggs
206ccdc0431SBen Skeggs /* Inhibit interrupts, and wait for idle. */
207ccdc0431SBen Skeggs if (pmu->func->enabled(pmu)) {
208ccdc0431SBen Skeggs nvkm_wr32(device, 0x10a014, 0x0000ffff);
209ccdc0431SBen Skeggs nvkm_msec(device, 2000,
210ccdc0431SBen Skeggs if (!nvkm_rd32(device, 0x10a04c))
211ccdc0431SBen Skeggs break;
212ccdc0431SBen Skeggs );
213ccdc0431SBen Skeggs }
214ccdc0431SBen Skeggs
215ccdc0431SBen Skeggs pmu->func->reset(pmu);
216ccdc0431SBen Skeggs
217ccdc0431SBen Skeggs /* Wait for IMEM/DMEM scrubbing to be complete. */
218ccdc0431SBen Skeggs nvkm_msec(device, 2000,
219ccdc0431SBen Skeggs if (!(nvkm_rd32(device, 0x10a10c) & 0x00000006))
220ccdc0431SBen Skeggs break;
221ccdc0431SBen Skeggs );
222ccdc0431SBen Skeggs
223da7d2062SBen Skeggs /* upload data segment */
224da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c0, 0x01000000);
225da7d2062SBen Skeggs for (i = 0; i < pmu->func->data.size / 4; i++)
226da7d2062SBen Skeggs nvkm_wr32(device, 0x10a1c4, pmu->func->data.data[i]);
227da7d2062SBen Skeggs
228da7d2062SBen Skeggs /* upload code segment */
229da7d2062SBen Skeggs nvkm_wr32(device, 0x10a180, 0x01000000);
230da7d2062SBen Skeggs for (i = 0; i < pmu->func->code.size / 4; i++) {
231da7d2062SBen Skeggs if ((i & 0x3f) == 0)
232da7d2062SBen Skeggs nvkm_wr32(device, 0x10a188, i >> 6);
233da7d2062SBen Skeggs nvkm_wr32(device, 0x10a184, pmu->func->code.data[i]);
234da7d2062SBen Skeggs }
235da7d2062SBen Skeggs
236da7d2062SBen Skeggs /* start it running */
237da7d2062SBen Skeggs nvkm_wr32(device, 0x10a10c, 0x00000000);
238da7d2062SBen Skeggs nvkm_wr32(device, 0x10a104, 0x00000000);
239da7d2062SBen Skeggs nvkm_wr32(device, 0x10a100, 0x00000002);
240da7d2062SBen Skeggs
241da7d2062SBen Skeggs /* wait for valid host->pmu ring configuration */
242da7d2062SBen Skeggs if (nvkm_msec(device, 2000,
243da7d2062SBen Skeggs if (nvkm_rd32(device, 0x10a4d0))
244da7d2062SBen Skeggs break;
245da7d2062SBen Skeggs ) < 0)
246da7d2062SBen Skeggs return -EBUSY;
247da7d2062SBen Skeggs pmu->send.base = nvkm_rd32(device, 0x10a4d0) & 0x0000ffff;
248da7d2062SBen Skeggs pmu->send.size = nvkm_rd32(device, 0x10a4d0) >> 16;
249da7d2062SBen Skeggs
250da7d2062SBen Skeggs /* wait for valid pmu->host ring configuration */
251da7d2062SBen Skeggs if (nvkm_msec(device, 2000,
252da7d2062SBen Skeggs if (nvkm_rd32(device, 0x10a4dc))
253da7d2062SBen Skeggs break;
254da7d2062SBen Skeggs ) < 0)
255da7d2062SBen Skeggs return -EBUSY;
256da7d2062SBen Skeggs pmu->recv.base = nvkm_rd32(device, 0x10a4dc) & 0x0000ffff;
257da7d2062SBen Skeggs pmu->recv.size = nvkm_rd32(device, 0x10a4dc) >> 16;
258da7d2062SBen Skeggs
259da7d2062SBen Skeggs nvkm_wr32(device, 0x10a010, 0x000000e0);
260da7d2062SBen Skeggs return 0;
261da7d2062SBen Skeggs }
262da7d2062SBen Skeggs
2632952a2b4SBen Skeggs const struct nvkm_falcon_func
2642952a2b4SBen Skeggs gt215_pmu_flcn = {
2652952a2b4SBen Skeggs };
2662952a2b4SBen Skeggs
267e2ca4e7dSBen Skeggs static const struct nvkm_pmu_func
268e2ca4e7dSBen Skeggs gt215_pmu = {
2692952a2b4SBen Skeggs .flcn = >215_pmu_flcn,
27021b13791SBen Skeggs .code.data = gt215_pmu_code,
27121b13791SBen Skeggs .code.size = sizeof(gt215_pmu_code),
27221b13791SBen Skeggs .data.data = gt215_pmu_data,
27321b13791SBen Skeggs .data.size = sizeof(gt215_pmu_data),
2746b1277c8SBen Skeggs .enabled = gt215_pmu_enabled,
275da7d2062SBen Skeggs .reset = gt215_pmu_reset,
276da7d2062SBen Skeggs .init = gt215_pmu_init,
277da7d2062SBen Skeggs .fini = gt215_pmu_fini,
278da7d2062SBen Skeggs .intr = gt215_pmu_intr,
279da7d2062SBen Skeggs .send = gt215_pmu_send,
280da7d2062SBen Skeggs .recv = gt215_pmu_recv,
281e2ca4e7dSBen Skeggs };
282e2ca4e7dSBen Skeggs
283989863d7SBen Skeggs static const struct nvkm_pmu_fwif
284989863d7SBen Skeggs gt215_pmu_fwif[] = {
285989863d7SBen Skeggs { -1, gf100_pmu_nofw, >215_pmu },
286989863d7SBen Skeggs {}
287989863d7SBen Skeggs };
288989863d7SBen Skeggs
289e2ca4e7dSBen Skeggs int
gt215_pmu_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_pmu ** ppmu)290e4b15b4cSBen Skeggs gt215_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
291e4b15b4cSBen Skeggs struct nvkm_pmu **ppmu)
292e2ca4e7dSBen Skeggs {
293e4b15b4cSBen Skeggs return nvkm_pmu_new_(gt215_pmu_fwif, device, type, inst, ppmu);
294e2ca4e7dSBen Skeggs }
295