| /openbmc/u-boot/board/freescale/m547xevb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m547xevb/m547xevb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m547xevb/mii.c MII init
14 - board/freescale/m547xevb/Makefile Makefile
15 - board/freescale/m547xevb/config.mk config make
16 - board/freescale/m547xevb/u-boot.lds Linker description
18 - arch/m68k/cpu/mcf547x_8x/cpu.c cpu specific code
19 - arch/m68k/cpu/mcf547x_8x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
20 - arch/m68k/cpu/mcf547x_8x/interrupts.c cpu specific interrupt support
21 - arch/m68k/cpu/mcf547x_8x/slicetimer.c Timer support
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| /openbmc/linux/Documentation/devicetree/bindings/x86/ |
| H A D | ce4100.txt | 2 ---------------------------
5 format: <vendor>,<chip>-<device>.
10 The CPU nodes
11 -------------
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu@0 {
18 device_type = "cpu";
23 cpu@2 {
24 device_type = "cpu";
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| /openbmc/linux/arch/mips/loongson2ef/common/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/pci.h>
8 #include <pci.h>
12 .name = "pci memory space",
19 .name = "pci io space",
36 * local to PCI mapping for CPU accessing PCI space in setup_pcimap()
37 * CPU address space [256M,448M] is window for accessing pci space in setup_pcimap()
38 * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] in setup_pcimap()
49 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] in setup_pcimap()
51 LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ in setup_pcimap()
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| /openbmc/linux/arch/x86/hyperv/ |
| H A D | irqdomain.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Irqdomain for Linux to run as the root partition on Microsoft Hypervisor.
11 #include <linux/pci.h>
16 int cpu, int vector, struct hv_interrupt_entry *entry) in hv_map_interrupt() argument
30 intr_desc = &input->interrupt_descriptor; in hv_map_interrupt()
32 input->partition_id = hv_current_partition_id; in hv_map_interrupt()
33 input->device_id = device_id.as_uint64; in hv_map_interrupt()
34 intr_desc->interrupt_type = HV_X64_INTERRUPT_TYPE_FIXED; in hv_map_interrupt()
35 intr_desc->vector_count = 1; in hv_map_interrupt()
36 intr_desc->target.vector = vector; in hv_map_interrupt()
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| /openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/ |
| H A D | pci_hw.h | 1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
79 * For Ethernet EMAD (Direct Route and non Direct Route) -
81 * For InfiniBand CTL - must be set if packet destination is local device
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
94 * Size of i-th scatter/gather entry, 0 if entry is unused.
96 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
99 * Physical address of i-th scatter/gather entry.
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| /openbmc/qemu/docs/system/arm/ |
| H A D | virt.rst | 4 The ``virt`` board is a platform which does not correspond to any
6 It is the recommended board type if you simply want to run
8 idiosyncrasies and limitations of a particular bit of real-world
14 to have the same behaviour as that of previous QEMU releases, so
16 ``virt-5.0`` machine type will behave like the ``virt`` machine from
17 the QEMU 5.0 release, and migration should work between ``virt-5.0``
18 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
19 is not guaranteed to work between different QEMU releases for
20 the non-versioned ``virt`` machine type.
27 - PCI/PCIe devices
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| /openbmc/linux/block/ |
| H A D | blk-mq-pci.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/blk-mq-pci.h>
8 #include <linux/pci.h>
11 #include "blk-mq.h"
14 * blk_mq_pci_map_queues - provide a default queue mapping for PCI device
15 * @qmap: CPU to hardware queue map.
16 * @pdev: PCI device associated with @set.
17 * @offset: Offset to use for the pci irq vector
19 * This function assumes the PCI device @pdev has at least as many available
21 * corresponding to each queue for it's affinity mask and built queue mapping
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| /openbmc/u-boot/board/freescale/m54455evb/ |
| H A D | README | 4 TsiChung Liew(Tsi-Chung.Liew@freescale.com)
12 - board/freescale/m54455evb/m54455evb.c Dram setup, IDE pre init, and PCI init
13 - board/freescale/m54455evb/flash.c Atmel and INTEL flash support
14 - board/freescale/m54455evb/Makefile Makefile
15 - board/freescale/m54455evb/config.mk config make
16 - board/freescale/m54455evb/u-boot.lds Linker description
18 - common/cmd_bdinfo.c Clock frequencies output
19 - common/cmd_mii.c mii support
21 - arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
22 - arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
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| /openbmc/linux/arch/mips/include/asm/mach-loongson2ef/ |
| H A D | pci.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 * we use address window2 to map cpu address space to pci space
19 * window2: cpu [1G, 2G] -> pci [1G, 2G]
20 * why not use window 0 & 1? because they are used by cpu when booting.
21 * window0: cpu [0, 256M] -> ddr [0, 256M]
22 * window1: cpu [256M, 512M] -> pci [256M, 512M]
30 #define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
32 #define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
37 /* this pci memory space is mapped by pcimap in pci.c */
|
| /openbmc/linux/arch/alpha/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
12 select DMA_OPS if PCI
14 select PCI_DOMAINS if PCI
15 select PCI_SYSCALL if PCI
42 The Alpha is a 64-bit general-purpose processor designed and
44 now Hewlett-Packard. The Alpha Linux project has a home page at
87 To find out what type of Alpha system you have, you may want to
91 Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
92 Alpha-XL XL-233, XL-266
102 LX164 AlphaPC164-LX
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
7 There are several things to be aware of that aren't at all obvious, like
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
21 typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
47 some performance penalty. Also, it is generally not possible to point to
49 is calculated using two DIMMs instead of one. Due to that, it is capable
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
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| H A D | device-io.rst | 10 Bus-Independent Device Accesses
20 and devices, allowing device drivers to be written independently of bus
26 Getting Access to the Device
27 ----------------------------
30 part of the CPU's address space is interpreted not as accesses to
31 memory, but as accesses to a device. Some architectures define devices
32 to be at a fixed address, but most have some method of discovering
33 devices. The PCI bus walk is a good example of such a scheme. This
34 document does not cover how to receive such an address, but assumes you
37 This address should not be used directly. Instead, to get an address
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| /openbmc/linux/arch/sparc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "64-bit kernel" if "$(ARCH)" = "sparc"
10 Say yes to build a 64-bit kernel - formerly known as sparc64
11 Say no to build a 32-bit kernel - formerly known as sparc
16 select ARCH_MIGHT_HAVE_PC_PARPORT if SPARC64 && PCI
42 select PCI_SYSCALL if PCI
102 select PCI_DOMAINS if PCI
157 bool "Symmetric multi-processing support"
159 This enables support for systems with more than one CPU. If you have
160 a system with only one CPU, say N. If you have a system with more
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| /openbmc/linux/Documentation/PCI/ |
| H A D | pci.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 How To Write Linux PCI Drivers
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
10 The world of PCI is vast and full of (mostly unpleasant) surprises.
11 Since each CPU architecture implements different chip-sets and PCI devices
12 have different requirements (erm, "features"), the result is the PCI support
14 tries to introduce all potential driver authors to Linux APIs for
15 PCI device drivers.
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
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| /openbmc/u-boot/arch/x86/ |
| H A D | Kconfig | 8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
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| /openbmc/qemu/docs/devel/migration/ |
| H A D | compatibility.rst | 5 ---------------------------------
15 - QEMU version
16 - machine type version
20 - qemu-system-x86_64 (v5.2), from now on qemu-5.2.
21 - qemu-system-x86_64 (v5.1), from now on qemu-5.1.
23 Related to this are the "latest" machine types defined on each of
26 - pc-q35-5.2 (newer one in qemu-5.2) from now on pc-5.2
27 - pc-q35-5.1 (newer one in qemu-5.1) from now on pc-5.1
29 First of all, migration is only supposed to work if you use the same
31 configuration needs to be the same also on source and destination.
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| /openbmc/linux/arch/mips/txx9/rbtx4927/ |
| H A D | setup.c | 7 * Copyright 2001-2002 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
20 * Copyright (C) 2000-2001 Toshiba Corporation
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
42 * with this program; if not, write to the Free Software Foundation, Inc.,
57 #include <asm/txx9/pci.h>
64 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB); in tx4927_pci_setup()
69 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) in tx4927_pci_setup()
74 /* Reset PCI Bus */ in tx4927_pci_setup()
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| /openbmc/u-boot/doc/ |
| H A D | README.mpc85xxcds | 2 --------------------------
4 The CDS family of boards consists of a PCI backplane called the
5 "Arcadia", a PCI-form-factor carrier card that plugs into a PCI slot,
6 and a CPU daughter card that bolts onto the daughter card.
9 applies to the 85xx CDS boards as well. In particular the toolchain,
14 Building U-Boot
15 ---------------
18 chip. You need to use binutils-2.14.tar.bz2 (or newer) from
21 The 85xx CDS code base is known to compile using:
22 gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
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| H A D | README.generic_usb_ohci | 1 Notes on the the generic USB-OHCI driver
6 cpu/board dependant initalization. This initalization has been moved
7 into cpu/board directories and are called via the hooks below.
10 ----------------------
16 - extern int board_usb_init(void);
17 - extern int usb_board_stop(void);
18 - extern int usb_cpu_init_fail(void);
20 CONFIG_SYS_USB_OHCI_CPU_INIT: call the cpu dependant hooks:
22 - extern int usb_cpu_init(void);
23 - extern int usb_cpu_stop(void);
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| /openbmc/linux/drivers/media/common/saa7146/ |
| H A D | saa7146_core.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 saa7146.o - driver for generic saa7146-based hardware
5 Copyright (C) 1998-2003 Michael Hunold <michael@mihu.de>
11 #include <media/drv-intf/saa7146.h>
56 /* wait for registers to be programmed */ in saa7146_wait_for_debi_done_sleep()
64 dev->name, __func__); in saa7146_wait_for_debi_done_sleep()
65 return -ETIMEDOUT; in saa7146_wait_for_debi_done_sleep()
70 /* wait for transfer to complete */ in saa7146_wait_for_debi_done_sleep()
79 dev->name, __func__); in saa7146_wait_for_debi_done_sleep()
80 return -ETIMEDOUT; in saa7146_wait_for_debi_done_sleep()
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| /openbmc/qemu/docs/devel/ |
| H A D | multi-process.rst | 1 Multi-process QEMU
6 This is the design document for multi-process QEMU. It does not
12 Please refer to the following wiki for latest details:
17 ability to run many VMs from different tenants in the same cloud
19 potentially use the hypervisor's access privileges to access data it is
22 QEMU can be susceptible to security attacks because it is a large,
23 monolithic program that provides many features to the VMs it services.
26 attack. Separating QEMU reduces the attack surface by aiding to
27 limit each component in the system to only access the resources that
28 it needs to perform its job.
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| /openbmc/linux/drivers/virt/nitro_enclaves/ |
| H A D | ne_misc_dev.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/pci.h>
20 * struct ne_mem_region - Entry in the enclave user space memory regions list.
36 * struct ne_enclave - Per-enclave data used for enclave lifetime management.
39 * @eventq: Wait queue used for out-of-band event notifications
40 * triggered from the PCI device event handler to
42 * @has_event: Variable used to determine if the out-of-band event
51 * total number of CPU cores available on the
53 * @nr_threads_per_core: The number of threads that a full CPU core has.
56 * @slot_uid: Slot unique id mapped to the enclave.
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| /openbmc/qemu/hw/hppa/ |
| H A D | machine.c | 3 * (C) Copyright 2018-2023 Helge Deller <deller@gmx.de>
10 #include "cpu.h"
13 #include "qemu/error-report.h"
20 #include "hw/char/serial-mm.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_device.h"
29 #include "hw/pci-host/astro.h"
30 #include "hw/pci-host/dino.h"
40 #define HPA_POWER_BUTTON (FIRMWARE_END - 0x10)
58 /* clear bit 31 to indicate that the power switch was pressed. */ in hppa_powerdown_req()
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| /openbmc/linux/Documentation/virt/ |
| H A D | ne_overview.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 that allows customers to carve out isolated compute environments within EC2
24 carved out of the primary VM. Each enclave is mapped to a process running in the
29 1. An enclave abstraction process - a user space process running in the primary
30 VM guest that uses the provided ioctl interface of the NE driver to spawn an
33 There is a NE emulated PCI device exposed to the primary VM. The driver for this
34 new PCI device is included in the NE driver.
36 The ioctl logic is mapped to PCI device commands e.g. the NE_START_ENCLAVE ioctl
37 maps to an enclave start PCI command. The PCI device commands are then
42 2. The enclave itself - a VM running on the same host as the primary VM that
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| /openbmc/qemu/hw/alpha/ |
| H A D | typhoon.c | 13 #include "hw/pci/pci_host.h"
14 #include "cpu.h"
19 #define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
20 #define TYPE_TYPHOON_IOMMU_MEMORY_REGION "typhoon-iommu-memory-region"
28 AlphaCPU *cpu[4]; member
62 static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) in cpu_irq_change() argument
64 /* If there are any non-masked interrupts, tell the cpu. */ in cpu_irq_change()
65 if (cpu != NULL) { in cpu_irq_change()
66 CPUState *cs = CPU(cpu); in cpu_irq_change()
79 CPUState *cpu = current_cpu; in cchip_read() local
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