Lines Matching +full:pci +full:- +full:to +full:- +full:cpu
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
30 arch_phys_memset() can be used for basic access to other memory.
33 bool "64-bit"
39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
40 experimental and many features are missing. U-Boot SPL starts up,
41 runs through the 16-bit and 32-bit init, then switches to 64-bit
42 mode and jumps to U-Boot proper.
83 # subarchitectures-specific options below
89 Select to build a U-Boot capable of supporting Intel MID
91 the PCI legacy interfaces.
99 # board-specific options below
109 # platform-specific options below
110 source "arch/x86/cpu/baytrail/Kconfig"
111 source "arch/x86/cpu/braswell/Kconfig"
112 source "arch/x86/cpu/broadwell/Kconfig"
113 source "arch/x86/cpu/coreboot/Kconfig"
114 source "arch/x86/cpu/ivybridge/Kconfig"
115 source "arch/x86/cpu/efi/Kconfig"
116 source "arch/x86/cpu/qemu/Kconfig"
117 source "arch/x86/cpu/quark/Kconfig"
118 source "arch/x86/cpu/queensbay/Kconfig"
119 source "arch/x86/cpu/tangier/Kconfig"
121 # architecture-specific options below
158 # The following options control where the 16-bit and 32-bit init lies
159 # If SPL is enabled then it normally holds this init code, and U-Boot proper
160 # is normally a 64-bit build.
162 # The 16-bit init refers to the reset vector and the small amount of code to
163 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
164 # or missing altogether if U-Boot is started from EFI or coreboot.
166 # The 32-bit init refers to processor init, running binary blobs including
167 # FSP, setting up interrupts and anything else that needs to be done in
168 # 32-bit code. It is normally in the same place as 16-bit init if that is
169 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
175 This is enabled when 16-bit init is in U-Boot proper
182 This is enabled when 16-bit init is in SPL
189 This is enabled when 32-bit init is in U-Boot proper
196 This is enabled when 32-bit init is in SPL
219 bool "Boot from a 32-bit program"
221 Define this to boot U-Boot from a 32-bit program which sets
222 the GDT differently. This can be used to boot directly from
224 payload-loading feature.
249 Select the size of the ROM chip you intend to flash U-Boot on.
251 The build system will take care of creating a u-boot.rom file
286 # Map the config names to an integer (KB).
296 # Map the config names to a hex value (bytes).
310 Newer higher-end devices have an Intel Management Engine (ME)
312 required for the platform to work. This enforces a particular
313 SPI flash format. You will need to supply the me.bin file in
320 often crash within U-Boot or the kernel. This option enables a
322 to work correctly. It is not exhaustive but can save time by
330 The filename of the file to use as flash descriptor in the
338 The filename of the file to use as Intel Management Engine in the
345 Select this option to add an Firmware Support Package binary to
346 the resulting U-Boot image. It is a binary blob which U-Boot uses
347 to set up SDRAM and other chipset specific initialization.
349 Note: Without this binary U-Boot will not be able to set up its
357 The filename of the file to use as Firmware Support Package binary
365 FSP is not Position Independent Code (PIC) and the whole FSP has to
368 Binary Configuration Tool (BCT) to do the rebase.
395 override this to n in their platform Kconfig files.
402 itself as reserved in the resource descriptor HOB. Select this to
403 tell U-Boot to do some additional work to ensure U-Boot relocation
405 FSP, otherwise the subsequent call to fsp_notify() will fail.
411 Enable this feature to cause MRC data to be cached in NV storage
412 to be used for speeding up boot time on future reboots and/or
416 please check FSP output HOB via U-Boot command 'fsp hob' to see
426 Select this option to add a System Agent binary to
427 the resulting U-Boot image. MRC stands for Memory Reference Code.
428 It is a binary blob which U-Boot uses to set up SDRAM.
430 Note: Without this binary U-Boot will not be able to set up its
439 MTRR (memory type range register) to turn on caching for the section
450 measured in KB. Typically this is set to 512, providing for 0.5MB
458 start address of the cache-as-RAM (CAR) area and the address varies
459 depending on the CPU. Once CAR is set up, read/write memory becomes
469 sets the size of the cache-as-RAM (CAR) area. Note that much of the
470 CAR space is required by the MRC. The CAR space available to U-Boot
471 is normally at the start and typically extends to 1/4 or 1/2 of the
486 Select this option to add a Reference Code binary to the resulting
487 U-Boot image. This is an Intel binary blob that handles system
491 broadwell) U-Boot will be missing some critical setup steps.
492 Various peripherals may fail to work.
498 Enable use of more than one CPU in U-Boot and the Operating System
499 when loaded. Each CPU will be started up and information can be
500 obtained using the 'cpu' command. If this option is disabled, then
501 only one CPU will be enabled regardless of the number of CPUs
509 When using multi-CPU chips it is possible for U-Boot to start up
510 more than one CPU. The stack memory used by all of these CPUs is
511 pre-allocated so at present U-Boot wants to know the maximum
512 number of CPUs that may be present. Set this to at least as high
514 each CPU).
521 Each additional CPU started by U-Boot requires its own stack. This
522 option sets the stack size used by each CPU and directly affects
530 scoped. i.e. turbo_enable() needs to be called on not just the
537 like to add to your ROM.
560 you would like to add to your ROM. This is normally required if you
562 later to initialize the integrated graphics device (IGD).
565 configuration information to the driver that is not discoverable
567 method here is to read EDID table from the attached monitor, over
569 configuration is related to display hardware and is available via
570 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
577 The filename of the file to use as Video BIOS Table (VBT) image
593 Turn on this option to enable a framebuffer driver when U-Boot is
594 using Video BIOS Table (VBT) image for FSP firmware to initialize
601 All x86 tables happen to like the address range from 0x0f0000
602 to 0x100000. We use 0xf0000 as the starting address to store
603 those tables, including PIRQ routing table, Multi-Processor
618 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
619 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
620 It specifies the interrupt router information as well how all the PCI
621 devices' interrupt pins are wired to PIRQs.
627 for platform firmware to pass information to the operating system
628 via static tables in memory. Kernel SFI support is required to
629 boot on SFI-only platforms. If you have ACPI tables then these are
632 U-Boot writes this table in write_sfi_table() just before booting
638 bool "Generate an MP (Multi-Processor) table"
641 Generate an MP (Multi-Processor) table for this board. The MP table
642 provides a way for the operating system to support for symmetric
653 by the operating system. It defines platform-independent interfaces
662 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
663 state where all system context is lost except system memory. U-Boot
667 registers, U-Boot needs to write the original value. When everything
668 is done, U-Boot needs to find out the wakeup vector provided by OSes
672 bool "Re-run VGA option ROMs on S3 resume"
675 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
679 graphics console won't work without VGA options ROMs. Set it to N
687 Estimated U-Boot's runtime stack size that needs to be reserved
696 Some newer chipsets offer more than four links, commonly up to PIRQH.
702 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
705 change it according to your needs.
711 This is the memory-mapped address of PCI configuration space, which
713 Mechanism (ECAM) with PCI Express. It can be set up almost
714 anywhere. Before it is set up, it is possible to access PCI
716 convenient. Using this, PCI can be scanned and configured. This
717 should be set to a region that does not conflict with memory
718 assigned to PCI devices - i.e. the memory and prefetch regions, as
719 passed to pci_set_region().
725 This is the size of memory-mapped address of PCI configuration space,
727 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
729 maximum number of PCI buses as defined by the PCI specification.
736 slave) interrupt controllers. Include this to have U-Boot set up
744 for catching interrupts and distributing them to one or more CPU
751 Intel ICH6 compatible chipset pinctrl driver. It needs to work
759 Include this to have U-Boot set up the timer correctly.
764 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
766 of coreboot/U-Boot. By turning on this option, U-Boot prepares
767 all the configuration tables that are necessary to boot SeaBIOS.
776 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
777 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
783 This is most likely due to a large ACPI DSDT table is used.