1df2634f4SSebastian Andrzej SiewiorCE4100 Device Tree Bindings 2df2634f4SSebastian Andrzej Siewior--------------------------- 3df2634f4SSebastian Andrzej Siewior 4df2634f4SSebastian Andrzej SiewiorThe CE4100 SoC uses for in core peripherals the following compatible 5df2634f4SSebastian Andrzej Siewiorformat: <vendor>,<chip>-<device>. 6df2634f4SSebastian Andrzej SiewiorMany of the "generic" devices like HPET or IO APIC have the ce4100 7df2634f4SSebastian Andrzej Siewiorname in their compatible property because they first appeared in this 8df2634f4SSebastian Andrzej SiewiorSoC. 9df2634f4SSebastian Andrzej Siewior 107f2e8584SIvan GorinovThe CPU nodes 117f2e8584SIvan Gorinov------------- 127f2e8584SIvan Gorinov 137f2e8584SIvan Gorinov cpus { 147f2e8584SIvan Gorinov #address-cells = <1>; 157f2e8584SIvan Gorinov #size-cells = <0>; 167f2e8584SIvan Gorinov 17df2634f4SSebastian Andrzej Siewior cpu@0 { 18df2634f4SSebastian Andrzej Siewior device_type = "cpu"; 19df2634f4SSebastian Andrzej Siewior compatible = "intel,ce4100"; 207f2e8584SIvan Gorinov reg = <0x00>; 21df2634f4SSebastian Andrzej Siewior }; 22df2634f4SSebastian Andrzej Siewior 237f2e8584SIvan Gorinov cpu@2 { 247f2e8584SIvan Gorinov device_type = "cpu"; 257f2e8584SIvan Gorinov compatible = "intel,ce4100"; 267f2e8584SIvan Gorinov reg = <0x02>; 277f2e8584SIvan Gorinov }; 287f2e8584SIvan Gorinov }; 297f2e8584SIvan Gorinov 307f2e8584SIvan GorinovA "cpu" node describes one logical processor (hardware thread). 317f2e8584SIvan Gorinov 327f2e8584SIvan GorinovRequired properties: 337f2e8584SIvan Gorinov 347f2e8584SIvan Gorinov- device_type 357f2e8584SIvan Gorinov Device type, must be "cpu". 367f2e8584SIvan Gorinov 377f2e8584SIvan Gorinov- reg 387f2e8584SIvan Gorinov Local APIC ID, the unique number assigned to each processor by 397f2e8584SIvan Gorinov system hardware. 40df2634f4SSebastian Andrzej Siewior 41df2634f4SSebastian Andrzej SiewiorThe SoC node 42df2634f4SSebastian Andrzej Siewior------------ 43df2634f4SSebastian Andrzej Siewior 44df2634f4SSebastian Andrzej SiewiorThis node describes the in-core peripherals. Required property: 45df2634f4SSebastian Andrzej Siewior compatible = "intel,ce4100-cp"; 46df2634f4SSebastian Andrzej Siewior 47df2634f4SSebastian Andrzej SiewiorThe PCI node 48df2634f4SSebastian Andrzej Siewior------------ 49df2634f4SSebastian Andrzej SiewiorThis node describes the PCI bus on the SoC. Its property should be 50df2634f4SSebastian Andrzej Siewior compatible = "intel,ce4100-pci", "pci"; 51df2634f4SSebastian Andrzej Siewior 52df2634f4SSebastian Andrzej SiewiorIf the OS is using the IO-APIC for interrupt routing then the reported 53df2634f4SSebastian Andrzej Siewiorinterrupt numbers for devices is no longer true. In order to obtain the 54df2634f4SSebastian Andrzej Siewiorcorrect interrupt number, the child node which represents the device has 55df2634f4SSebastian Andrzej Siewiorto contain the interrupt property. Besides the interrupt property it has 56df2634f4SSebastian Andrzej Siewiorto contain at least the reg property containing the PCI bus address and 57df2634f4SSebastian Andrzej Siewiorcompatible property according to "PCI Bus Binding Revision 2.1". 58