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/openbmc/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_run_32r5eb.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
[all …]
H A Dtest_msa_run_32r5el.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml30 | +----+------|- MIPS P5600 cores
48 to create a clock for the MIPS P5600 cores, the embedded DDR controller,
78 clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
H A Dbaikal,bt1-ccu-div.yaml33 | +----+------|- MIPS P5600 cores
/openbmc/qemu/docs/system/
H A Dcpu-models-mips.rst.inc19 ``P5600``
20 MIPS32 Processor (P5600, 2014)
/openbmc/qemu/linux-user/mips/
H A Dtarget_elf.h16 return "P5600"; in cpu_get_model()
/openbmc/linux/arch/mips/include/asm/
H A Dvermagic.h52 #define MODULE_PROC_FAMILY "P5600 "
H A Dmipsregs.h685 /* Config6 feature bits for proAptiv/P5600 */
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dbaikal,bt1-l2-ctl.yaml15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dbaikal,bt1-axi.yaml15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
/openbmc/linux/drivers/memory/
H A DKconfig72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
/openbmc/linux/drivers/bus/
H A DKconfig62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
/openbmc/linux/arch/mips/
H A DKconfig1510 bool "MIPS Warrior P5600"
1522 Choose this option to build a kernel for MIPS Warrior P5600 CPU.
1525 level features like up to six P5600 calculation cores, CM2 with L2
1711 Addressing (XPA) on your MIPS32 core (such as P5600 series). The
H A DMakefile163 cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg
/openbmc/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c1656 /* P5600 */
1939 mipspmu.name = "mips/P5600"; in init_hw_perf_events()
H A Dcpu-probe.c1413 __cpu_name[cpu] = "MIPS P5600"; in cpu_probe_mips()
/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc427 .name = "P5600",
/openbmc/linux/arch/mips/kvm/
H A Dvz.c996 * P5600 generates GPSI on guest MTC0 LLAddr. in kvm_vz_gpsi_cop0()