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/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
76 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
[all …]
/openbmc/openbmc/poky/bitbake/lib/bb/fetch2/
H A Dosc.py7 Bitbake "Fetch" implementation for osc (Opensuse build service client).
23 class Osc(FetchMethod): class
29 Check to see if a given url can be fetched with osc.
31 return ud.type in ['osc']
39 # Create paths to osc checkouts
40 oscdir = d.getVar("OSCDIR") or (d.getVar("DL_DIR") + "/osc")
64 basecmd = d.getVar("FETCHCMD_osc") or "/usr/bin/env osc"
84 raise FetchError("Invalid osc command %s" % command, ud.url)
97 raise FetchError("Unable to parse osc response", ud.url)
107 return "osc:%s%s.%s.%s" % (ud.host, slash_re.sub(".", ud.path), name, rev)
/openbmc/u-boot/drivers/clk/
H A Dclk_vexpress_osc.c18 u8 osc; member
30 data = CLK_FUNCTION | priv->osc; in vexpress_osc_clk_get_rate()
53 buffer[0] = CLK_FUNCTION | priv->osc; in vexpress_osc_clk_set_rate()
90 priv->osc = values[1]; in vexpress_osc_clk_probe()
92 priv->osc, priv->rate_min, priv->rate_max); in vexpress_osc_clk_probe()
98 { .compatible = "arm,vexpress-osc", },
H A Dclk_stm32mp1.c237 * they are used as index in osc[] as entry point
414 ulong osc[NB_OSC]; member
745 (u32)priv->osc[idx], priv->osc[idx] / 1000); in stm32mp1_clk_get_fixed()
747 return priv->osc[idx]; in stm32mp1_clk_get_fixed()
1203 pr_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", in stm32mp1_osc_wait()
1625 if (priv->osc[_LSI]) in stm32mp1_clktree()
1628 if (priv->osc[_LSE]) { in stm32mp1_clktree()
1641 if (priv->osc[_HSE]) { in stm32mp1_clktree()
1668 if (priv->osc[_HSI]) { in stm32mp1_clktree()
1669 stm32mp1_hsidiv(rcc, priv->osc[_HSI]); in stm32mp1_clktree()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
135 104 osc
184 osc: clock {
205 clocks = <&clk_32k> <&osc>;
/openbmc/u-boot/arch/xtensa/dts/
H A Dxtfpga.dtsi39 osc: main-oscillator { label
66 clocks = <&osc>;
75 clocks = <&osc>;
95 clocks = <&osc>;
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_pll_config.c128 const unsigned int cm_get_osc_clk_hz(const int osc) in cm_get_osc_clk_hz() argument
130 if (osc == 1) in cm_get_osc_clk_hz()
132 else if (osc == 2) in cm_get_osc_clk_hz()
/openbmc/u-boot/board/silica/pengwyn/
H A Dboard.c70 #define OSC (V_OSCK/1000000) macro
72 266, OSC-1, 1, -1, -1, -1, -1};
74 303, OSC-1, 1, -1, -1, -1, -1};
76 400, OSC-1, 1, -1, -1, -1, -1};
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h122 /* SCG System OSC Control Status Register */
136 /* SCG RTC OSC Control Status Register */
187 /* 0: Sys-OSC, 1: FIRC */
272 u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
273 u32 soscdiv; /* System OSC Divide Register */
296 u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
74 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
99 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
101 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
116 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
101 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
118 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
[all …]
/openbmc/u-boot/board/eets/pdu001/
H A Dboard.c184 #define OSC (V_OSCK / 1000000) macro
186 266, OSC - 1, 1, -1, -1, -1, -1};
188 303, OSC - 1, 1, -1, -1, -1, -1};
190 400, OSC - 1, 1, -1, -1, -1, -1};
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c27 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
61 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
63 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
65 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
66 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
67 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
68 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
587 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ in clock_early_init()
592 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ in clock_early_init()
597 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ in clock_early_init()
H A Dwarmboot_avp.c148 /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */ in wb_start()
152 * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and in wb_start()
153 * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz. in wb_start()
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
/openbmc/qemu/hw/misc/
H A Dsifive_e_prci.c53 /* OSC stays ready */ in sifive_e_prci_write()
58 /* OSC stays ready */ in sifive_e_prci_write()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dtimer.c32 #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
84 * For DL/S, SX, UL, ULL, SLL set 24Mhz OSC in timer_init()
/openbmc/u-boot/board/gumstix/pepper/
H A Dboard.c35 #define OSC (V_OSCK/1000000) macro
65 const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
98 const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c17 #define OSC (V_OSCK/1000000) macro
62 CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
64 1000, OSC-1, -1, -1, 10, 8, 4};
234 /* Select the Master osc 24 MHZ as Timer2 clock source */ in enable_basic_clocks()
/openbmc/u-boot/board/birdland/bav335x/
H A Dboard.c173 #define OSC (V_OSCK/1000000) macro
175 266, OSC-1, 1, -1, -1, -1, -1};
177 303, OSC-1, 1, -1, -1, -1, -1};
179 400, OSC-1, 1, -1, -1, -1, -1};
/openbmc/openbmc/poky/meta/classes/
H A Down-mirrors.bbclass15 osc://.*/.* ${SOURCE_MIRROR_URL} \
/openbmc/u-boot/drivers/clk/at91/
H A Dclk-main.c48 .name = "at91sam9x5-main-osc-clk",
/openbmc/u-boot/board/BuR/brppt1/
H A Dboard.c75 #define OSC (V_OSCK/1000000) macro
76 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
/openbmc/openbmc/meta-openembedded/meta-oe/lib/oeqa/selftest/cases/
H A Dmeta_oe_sources.py23 osc://.*/.* http://sources.openembedded.org/ \\n \\

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