| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | imx1-clock.yaml | 7 title: Freescale i.MX1 CPUs Clock Controller
15 for the full list of i.MX1 clock IDs.
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-pllv1.c | 22 * PLL clock version 1, found on i.MX1/21/25/27/31/35
66 * frequency. PLLs with this register layout can be found on i.MX1, in clk_pllv1_recalc_rate()
84 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit in clk_pllv1_recalc_rate()
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| /openbmc/linux/arch/arm/mach-imx/ |
| H A D | Kconfig | 61 bool "i.MX1 support"
66 This enables support for Freescale i.MX1 processor
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| H A D | mach-imx1.c | 21 DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)")
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| H A D | hardware.h | 40 * mx1:
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| /openbmc/linux/drivers/gpu/drm/imx/lcdc/ |
| H A D | Kconfig | 7 Found on i.MX1, i.MX21, i.MX25 and i.MX27.
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-imx-gpt.c | 22 * - MX1/MXL
28 GPT_TYPE_IMX1, /* i.MX1 */
39 /* MX1, MX21, MX27 */
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| /openbmc/linux/Documentation/devicetree/bindings/pwm/ |
| H A D | imx-pwm.yaml | 18 Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx1-ads.dts | 10 model = "Freescale MX1 ADS";
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| H A D | imx1-pinfunc.h | 29 * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32
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| /openbmc/linux/Documentation/devicetree/bindings/display/imx/ |
| H A D | fsl,imx-lcdc.yaml | 7 title: Freescale i.MX LCD Controller, found on i.MX1, i.MX21, i.MX25 and i.MX27
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | mxcmmc.c | 3 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
4 * Unlike the hardware found on MX1, this hardware just works and does
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| /openbmc/linux/drivers/watchdog/ |
| H A D | imx2_wdt.c | 11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
13 * MX1: MX2+:
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | imx-weim.txt | 62 For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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| /openbmc/linux/drivers/soc/imx/ |
| H A D | soc-imx.c | 57 soc_id = "i.MX1"; in imx_soc_device_init()
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| /openbmc/linux/drivers/pwm/ |
| H A D | Kconfig | 244 tristate "i.MX1 PWM support"
248 Generic PWM framework driver for i.MX1 and i.MX21
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| /openbmc/linux/drivers/pinctrl/freescale/ |
| H A D | pinctrl-imx1.c | 3 // i.MX1 pinctrl driver based on imx pinmux core
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| H A D | pinctrl-imx1-core.c | 39 * MX1 register offsets
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| /openbmc/linux/drivers/bus/ |
| H A D | imx-weim.c | 74 /* i.MX1/21 */
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | mxcmmc.c | 6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
7 * Unlike the hardware found on MX1, this hardware just works and does
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| /openbmc/linux/drivers/tty/serial/ |
| H A D | imx.c | 53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
178 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
2450 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later in imx_uart_probe()
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| /openbmc/linux/drivers/dma/ |
| H A D | Kconfig | 271 Freescale i.MX1/21/27 chips.
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| /openbmc/linux/drivers/gpio/ |
| H A D | gpio-mxc.c | 276 /* MX1 and MX3 has one interrupt *per* gpio port */
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| /openbmc/linux/arch/arm/ |
| H A D | Kconfig.debug | 405 bool "i.MX1 Debug UART"
409 on i.MX1.
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| /openbmc/linux/drivers/mfd/ |
| H A D | sm501.c | 173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", in sm501_dump_clk()
182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", in sm501_dump_clk()
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