1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+
2ab4382d2SGreg Kroah-Hartman /*
3f890cef2SUwe Kleine-König * Driver for Motorola/Freescale IMX serial ports
4ab4382d2SGreg Kroah-Hartman *
5ab4382d2SGreg Kroah-Hartman * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6ab4382d2SGreg Kroah-Hartman *
7ab4382d2SGreg Kroah-Hartman * Author: Sascha Hauer <sascha@saschahauer.de>
8ab4382d2SGreg Kroah-Hartman * Copyright (C) 2004 Pengutronix
9ab4382d2SGreg Kroah-Hartman */
10ab4382d2SGreg Kroah-Hartman
11ab4382d2SGreg Kroah-Hartman #include <linux/module.h>
12ab4382d2SGreg Kroah-Hartman #include <linux/ioport.h>
13ab4382d2SGreg Kroah-Hartman #include <linux/init.h>
14ab4382d2SGreg Kroah-Hartman #include <linux/console.h>
15ab4382d2SGreg Kroah-Hartman #include <linux/sysrq.h>
16ab4382d2SGreg Kroah-Hartman #include <linux/platform_device.h>
17ab4382d2SGreg Kroah-Hartman #include <linux/tty.h>
18ab4382d2SGreg Kroah-Hartman #include <linux/tty_flip.h>
19ab4382d2SGreg Kroah-Hartman #include <linux/serial_core.h>
20ab4382d2SGreg Kroah-Hartman #include <linux/serial.h>
21ab4382d2SGreg Kroah-Hartman #include <linux/clk.h>
22ab4382d2SGreg Kroah-Hartman #include <linux/delay.h>
23bd78ecd6SAhmad Fatoum #include <linux/ktime.h>
24fcfed1beSAnson Huang #include <linux/pinctrl/consumer.h>
25ab4382d2SGreg Kroah-Hartman #include <linux/rational.h>
26ab4382d2SGreg Kroah-Hartman #include <linux/slab.h>
2722698aa2SShawn Guo #include <linux/of.h>
28e32a9f8fSSachin Kamat #include <linux/io.h>
29*982ae337SEsben Haabendal #include <linux/iopoll.h>
30b4cdc8f6SHuang Shijie #include <linux/dma-mapping.h>
31ab4382d2SGreg Kroah-Hartman
32ab4382d2SGreg Kroah-Hartman #include <asm/irq.h>
33c6547c2eSSascha Hauer #include <linux/dma/imx-dma.h>
34ab4382d2SGreg Kroah-Hartman
3558362d5bSUwe Kleine-König #include "serial_mctrl_gpio.h"
3658362d5bSUwe Kleine-König
37ab4382d2SGreg Kroah-Hartman /* Register definitions */
38ab4382d2SGreg Kroah-Hartman #define URXD0 0x0 /* Receiver Register */
39ab4382d2SGreg Kroah-Hartman #define URTX0 0x40 /* Transmitter Register */
40ab4382d2SGreg Kroah-Hartman #define UCR1 0x80 /* Control Register 1 */
41ab4382d2SGreg Kroah-Hartman #define UCR2 0x84 /* Control Register 2 */
42ab4382d2SGreg Kroah-Hartman #define UCR3 0x88 /* Control Register 3 */
43ab4382d2SGreg Kroah-Hartman #define UCR4 0x8c /* Control Register 4 */
44ab4382d2SGreg Kroah-Hartman #define UFCR 0x90 /* FIFO Control Register */
45ab4382d2SGreg Kroah-Hartman #define USR1 0x94 /* Status Register 1 */
46ab4382d2SGreg Kroah-Hartman #define USR2 0x98 /* Status Register 2 */
47ab4382d2SGreg Kroah-Hartman #define UESC 0x9c /* Escape Character Register */
48ab4382d2SGreg Kroah-Hartman #define UTIM 0xa0 /* Escape Timer Register */
49ab4382d2SGreg Kroah-Hartman #define UBIR 0xa4 /* BRM Incremental Register */
50ab4382d2SGreg Kroah-Hartman #define UBMR 0xa8 /* BRM Modulator Register */
51ab4382d2SGreg Kroah-Hartman #define UBRC 0xac /* Baud Rate Count Register */
52fe6b540aSShawn Guo #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53fe6b540aSShawn Guo #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54fe6b540aSShawn Guo #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55ab4382d2SGreg Kroah-Hartman
56ab4382d2SGreg Kroah-Hartman /* UART Control Register Bit Fields.*/
5755d8693aSJiada Wang #define URXD_DUMMY_READ (1<<16)
58ab4382d2SGreg Kroah-Hartman #define URXD_CHARRDY (1<<15)
59ab4382d2SGreg Kroah-Hartman #define URXD_ERR (1<<14)
60ab4382d2SGreg Kroah-Hartman #define URXD_OVRRUN (1<<13)
61ab4382d2SGreg Kroah-Hartman #define URXD_FRMERR (1<<12)
62ab4382d2SGreg Kroah-Hartman #define URXD_BRK (1<<11)
63ab4382d2SGreg Kroah-Hartman #define URXD_PRERR (1<<10)
6426c47412SDirk Behme #define URXD_RX_DATA (0xFF<<0)
6525985edcSLucas De Marchi #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66ab4382d2SGreg Kroah-Hartman #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67ab4382d2SGreg Kroah-Hartman #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68ab4382d2SGreg Kroah-Hartman #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69b4cdc8f6SHuang Shijie #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70ab4382d2SGreg Kroah-Hartman #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71302e8dccSUwe Kleine-König #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72ab4382d2SGreg Kroah-Hartman #define UCR1_IREN (1<<7) /* Infrared interface enable */
73ab4382d2SGreg Kroah-Hartman #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74ab4382d2SGreg Kroah-Hartman #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75ab4382d2SGreg Kroah-Hartman #define UCR1_SNDBRK (1<<4) /* Send break */
76302e8dccSUwe Kleine-König #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77fe6b540aSShawn Guo #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78b4cdc8f6SHuang Shijie #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79ab4382d2SGreg Kroah-Hartman #define UCR1_DOZE (1<<1) /* Doze */
80ab4382d2SGreg Kroah-Hartman #define UCR1_UARTEN (1<<0) /* UART enabled */
81ab4382d2SGreg Kroah-Hartman #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82ab4382d2SGreg Kroah-Hartman #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83ab4382d2SGreg Kroah-Hartman #define UCR2_CTSC (1<<13) /* CTS pin control */
84ab4382d2SGreg Kroah-Hartman #define UCR2_CTS (1<<12) /* Clear to send */
85ab4382d2SGreg Kroah-Hartman #define UCR2_ESCEN (1<<11) /* Escape enable */
86ab4382d2SGreg Kroah-Hartman #define UCR2_PREN (1<<8) /* Parity enable */
87ab4382d2SGreg Kroah-Hartman #define UCR2_PROE (1<<7) /* Parity odd/even */
88ab4382d2SGreg Kroah-Hartman #define UCR2_STPB (1<<6) /* Stop */
89ab4382d2SGreg Kroah-Hartman #define UCR2_WS (1<<5) /* Word size */
90ab4382d2SGreg Kroah-Hartman #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
9101f56abdSSaleem Abdulrasool #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92ab4382d2SGreg Kroah-Hartman #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93ab4382d2SGreg Kroah-Hartman #define UCR2_RXEN (1<<1) /* Receiver enabled */
94ab4382d2SGreg Kroah-Hartman #define UCR2_SRST (1<<0) /* SW reset */
95ab4382d2SGreg Kroah-Hartman #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96ab4382d2SGreg Kroah-Hartman #define UCR3_PARERREN (1<<12) /* Parity enable */
97ab4382d2SGreg Kroah-Hartman #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98ab4382d2SGreg Kroah-Hartman #define UCR3_DSR (1<<10) /* Data set ready */
99ab4382d2SGreg Kroah-Hartman #define UCR3_DCD (1<<9) /* Data carrier detect */
100ab4382d2SGreg Kroah-Hartman #define UCR3_RI (1<<8) /* Ring indicator */
101b38cb7d2SFabio Estevam #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102ab4382d2SGreg Kroah-Hartman #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103ab4382d2SGreg Kroah-Hartman #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104ab4382d2SGreg Kroah-Hartman #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
10527e16501SUwe Kleine-König #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106fe6b540aSShawn Guo #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107ab4382d2SGreg Kroah-Hartman #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108ab4382d2SGreg Kroah-Hartman #define UCR3_BPEN (1<<0) /* Preset registers enable */
109ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110ab4382d2SGreg Kroah-Hartman #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111ab4382d2SGreg Kroah-Hartman #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112ab4382d2SGreg Kroah-Hartman #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113ab4382d2SGreg Kroah-Hartman #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114ab4382d2SGreg Kroah-Hartman #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115b4cdc8f6SHuang Shijie #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116ab4382d2SGreg Kroah-Hartman #define UCR4_IRSC (1<<5) /* IR special case */
117ab4382d2SGreg Kroah-Hartman #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118ab4382d2SGreg Kroah-Hartman #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119ab4382d2SGreg Kroah-Hartman #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120ab4382d2SGreg Kroah-Hartman #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121ab4382d2SGreg Kroah-Hartman #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
1227be0670fSDirk Behme #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124ab4382d2SGreg Kroah-Hartman #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125ab4382d2SGreg Kroah-Hartman #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126ab4382d2SGreg Kroah-Hartman #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127ab4382d2SGreg Kroah-Hartman #define USR1_RTSS (1<<14) /* RTS pin status */
128ab4382d2SGreg Kroah-Hartman #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129ab4382d2SGreg Kroah-Hartman #define USR1_RTSD (1<<12) /* RTS delta */
130ab4382d2SGreg Kroah-Hartman #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131ab4382d2SGreg Kroah-Hartman #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132ab4382d2SGreg Kroah-Hartman #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
13386a04ba6SLucas Stach #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
13427e16501SUwe Kleine-König #define USR1_DTRD (1<<7) /* DTR Delta */
135ab4382d2SGreg Kroah-Hartman #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136ab4382d2SGreg Kroah-Hartman #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137ab4382d2SGreg Kroah-Hartman #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138ab4382d2SGreg Kroah-Hartman #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139ab4382d2SGreg Kroah-Hartman #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140ab4382d2SGreg Kroah-Hartman #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141ab4382d2SGreg Kroah-Hartman #define USR2_IDLE (1<<12) /* Idle condition */
14290ebc483SUwe Kleine-König #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
14390ebc483SUwe Kleine-König #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144ab4382d2SGreg Kroah-Hartman #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145ab4382d2SGreg Kroah-Hartman #define USR2_WAKE (1<<7) /* Wake */
14690ebc483SUwe Kleine-König #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147ab4382d2SGreg Kroah-Hartman #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148ab4382d2SGreg Kroah-Hartman #define USR2_TXDC (1<<3) /* Transmitter complete */
149ab4382d2SGreg Kroah-Hartman #define USR2_BRCD (1<<2) /* Break condition */
150ab4382d2SGreg Kroah-Hartman #define USR2_ORE (1<<1) /* Overrun error */
151ab4382d2SGreg Kroah-Hartman #define USR2_RDR (1<<0) /* Recv data ready */
152ab4382d2SGreg Kroah-Hartman #define UTS_FRCPERR (1<<13) /* Force parity error */
153ab4382d2SGreg Kroah-Hartman #define UTS_LOOP (1<<12) /* Loop tx and rx */
154ab4382d2SGreg Kroah-Hartman #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155ab4382d2SGreg Kroah-Hartman #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156ab4382d2SGreg Kroah-Hartman #define UTS_TXFULL (1<<4) /* TxFIFO full */
157ab4382d2SGreg Kroah-Hartman #define UTS_RXFULL (1<<3) /* RxFIFO full */
158ab4382d2SGreg Kroah-Hartman #define UTS_SOFTRST (1<<0) /* Software reset */
159ab4382d2SGreg Kroah-Hartman
160ab4382d2SGreg Kroah-Hartman /* We've been assigned a range on the "Low-density serial ports" major */
161ab4382d2SGreg Kroah-Hartman #define SERIAL_IMX_MAJOR 207
162ab4382d2SGreg Kroah-Hartman #define MINOR_START 16
163ab4382d2SGreg Kroah-Hartman #define DEV_NAME "ttymxc"
164ab4382d2SGreg Kroah-Hartman
165ab4382d2SGreg Kroah-Hartman /*
166ab4382d2SGreg Kroah-Hartman * This determines how often we check the modem status signals
167ab4382d2SGreg Kroah-Hartman * for any change. They generally aren't connected to an IRQ
168ab4382d2SGreg Kroah-Hartman * so we have to poll them. We also check immediately before
169ab4382d2SGreg Kroah-Hartman * filling the TX fifo incase CTS has been dropped.
170ab4382d2SGreg Kroah-Hartman */
171ab4382d2SGreg Kroah-Hartman #define MCTRL_TIMEOUT (250*HZ/1000)
172ab4382d2SGreg Kroah-Hartman
173ab4382d2SGreg Kroah-Hartman #define DRIVER_NAME "IMX-uart"
174ab4382d2SGreg Kroah-Hartman
175ab4382d2SGreg Kroah-Hartman #define UART_NR 8
176ab4382d2SGreg Kroah-Hartman
177f95661b2SUwe Kleine-König /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178fe6b540aSShawn Guo enum imx_uart_type {
179fe6b540aSShawn Guo IMX1_UART,
180fe6b540aSShawn Guo IMX21_UART,
1811c06bde6SMartyn Welch IMX53_UART,
182a496e628SHuang Shijie IMX6Q_UART,
183fe6b540aSShawn Guo };
184fe6b540aSShawn Guo
185fe6b540aSShawn Guo /* device type dependent stuff */
186fe6b540aSShawn Guo struct imx_uart_data {
187fe6b540aSShawn Guo unsigned uts_reg;
188fe6b540aSShawn Guo enum imx_uart_type devtype;
189fe6b540aSShawn Guo };
190fe6b540aSShawn Guo
191cb1a6092SUwe Kleine-König enum imx_tx_state {
192cb1a6092SUwe Kleine-König OFF,
193cb1a6092SUwe Kleine-König WAIT_AFTER_RTS,
194cb1a6092SUwe Kleine-König SEND,
195cb1a6092SUwe Kleine-König WAIT_AFTER_SEND,
196cb1a6092SUwe Kleine-König };
197cb1a6092SUwe Kleine-König
198ab4382d2SGreg Kroah-Hartman struct imx_port {
199ab4382d2SGreg Kroah-Hartman struct uart_port port;
200ab4382d2SGreg Kroah-Hartman struct timer_list timer;
201ab4382d2SGreg Kroah-Hartman unsigned int old_status;
202ab4382d2SGreg Kroah-Hartman unsigned int have_rtscts:1;
2037b7e8e8eSFabio Estevam unsigned int have_rtsgpio:1;
20420ff2fe6SHuang Shijie unsigned int dte_mode:1;
2055a08a487SGeorge Hilliard unsigned int inverted_tx:1;
2065a08a487SGeorge Hilliard unsigned int inverted_rx:1;
2073a9465faSSascha Hauer struct clk *clk_ipg;
2083a9465faSSascha Hauer struct clk *clk_per;
2097d0b066fSUwe Kleine-König const struct imx_uart_data *devdata;
210b4cdc8f6SHuang Shijie
21158362d5bSUwe Kleine-König struct mctrl_gpios *gpios;
21258362d5bSUwe Kleine-König
213496a4471SSergey Organov /* counter to stop 0xff flood */
214496a4471SSergey Organov int idle_counter;
215496a4471SSergey Organov
216b4cdc8f6SHuang Shijie /* DMA fields */
217b4cdc8f6SHuang Shijie unsigned int dma_is_enabled:1;
218b4cdc8f6SHuang Shijie unsigned int dma_is_rxing:1;
219b4cdc8f6SHuang Shijie unsigned int dma_is_txing:1;
220b4cdc8f6SHuang Shijie struct dma_chan *dma_chan_rx, *dma_chan_tx;
221b4cdc8f6SHuang Shijie struct scatterlist rx_sgl, tx_sgl[2];
222b4cdc8f6SHuang Shijie void *rx_buf;
2239d297239SNandor Han struct circ_buf rx_ring;
224db0a196bSFabien Lahoudere unsigned int rx_buf_size;
225db0a196bSFabien Lahoudere unsigned int rx_period_length;
2269d297239SNandor Han unsigned int rx_periods;
2279d297239SNandor Han dma_cookie_t rx_cookie;
2287cb92fd2SHuang Shijie unsigned int tx_bytes;
229b4cdc8f6SHuang Shijie unsigned int dma_tx_nents;
23090bb6bd3SShenwei Wang unsigned int saved_reg[10];
231c868cbb7SEduardo Valentin bool context_saved;
232cb1a6092SUwe Kleine-König
233cb1a6092SUwe Kleine-König enum imx_tx_state tx_state;
234bd78ecd6SAhmad Fatoum struct hrtimer trigger_start_tx;
235bd78ecd6SAhmad Fatoum struct hrtimer trigger_stop_tx;
236ab4382d2SGreg Kroah-Hartman };
237ab4382d2SGreg Kroah-Hartman
2380ad5a814SDirk Behme struct imx_port_ucrs {
2390ad5a814SDirk Behme unsigned int ucr1;
2400ad5a814SDirk Behme unsigned int ucr2;
2410ad5a814SDirk Behme unsigned int ucr3;
2420ad5a814SDirk Behme };
2430ad5a814SDirk Behme
244fe6b540aSShawn Guo static struct imx_uart_data imx_uart_devdata[] = {
245fe6b540aSShawn Guo [IMX1_UART] = {
246fe6b540aSShawn Guo .uts_reg = IMX1_UTS,
247fe6b540aSShawn Guo .devtype = IMX1_UART,
248fe6b540aSShawn Guo },
249fe6b540aSShawn Guo [IMX21_UART] = {
250fe6b540aSShawn Guo .uts_reg = IMX21_UTS,
251fe6b540aSShawn Guo .devtype = IMX21_UART,
252fe6b540aSShawn Guo },
2531c06bde6SMartyn Welch [IMX53_UART] = {
2541c06bde6SMartyn Welch .uts_reg = IMX21_UTS,
2551c06bde6SMartyn Welch .devtype = IMX53_UART,
2561c06bde6SMartyn Welch },
257a496e628SHuang Shijie [IMX6Q_UART] = {
258a496e628SHuang Shijie .uts_reg = IMX21_UTS,
259a496e628SHuang Shijie .devtype = IMX6Q_UART,
260a496e628SHuang Shijie },
261fe6b540aSShawn Guo };
262fe6b540aSShawn Guo
263ad3d4fdcSSanjeev Sharma static const struct of_device_id imx_uart_dt_ids[] = {
264a496e628SHuang Shijie { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
2651c06bde6SMartyn Welch { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
26622698aa2SShawn Guo { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
26722698aa2SShawn Guo { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
26822698aa2SShawn Guo { /* sentinel */ }
26922698aa2SShawn Guo };
27022698aa2SShawn Guo MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
27122698aa2SShawn Guo
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)272f2d9fbb6SSergey Organov static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
27327c84426SUwe Kleine-König {
27427c84426SUwe Kleine-König writel(val, sport->port.membase + offset);
27527c84426SUwe Kleine-König }
27627c84426SUwe Kleine-König
imx_uart_readl(struct imx_port * sport,u32 offset)277f2d9fbb6SSergey Organov static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
27827c84426SUwe Kleine-König {
27927c84426SUwe Kleine-König return readl(sport->port.membase + offset);
28027c84426SUwe Kleine-König }
28127c84426SUwe Kleine-König
imx_uart_uts_reg(struct imx_port * sport)2829d1a50a2SUwe Kleine-König static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
283fe6b540aSShawn Guo {
284fe6b540aSShawn Guo return sport->devdata->uts_reg;
285fe6b540aSShawn Guo }
286fe6b540aSShawn Guo
imx_uart_is_imx1(struct imx_port * sport)2879d1a50a2SUwe Kleine-König static inline int imx_uart_is_imx1(struct imx_port *sport)
288fe6b540aSShawn Guo {
289fe6b540aSShawn Guo return sport->devdata->devtype == IMX1_UART;
290fe6b540aSShawn Guo }
291fe6b540aSShawn Guo
292ab4382d2SGreg Kroah-Hartman /*
29344a75411Sfabio.estevam@freescale.com * Save and restore functions for UCR1, UCR2 and UCR3 registers
29444a75411Sfabio.estevam@freescale.com */
2950db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)2969d1a50a2SUwe Kleine-König static void imx_uart_ucrs_save(struct imx_port *sport,
29744a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr)
29844a75411Sfabio.estevam@freescale.com {
29944a75411Sfabio.estevam@freescale.com /* save control registers */
30027c84426SUwe Kleine-König ucr->ucr1 = imx_uart_readl(sport, UCR1);
30127c84426SUwe Kleine-König ucr->ucr2 = imx_uart_readl(sport, UCR2);
30227c84426SUwe Kleine-König ucr->ucr3 = imx_uart_readl(sport, UCR3);
30344a75411Sfabio.estevam@freescale.com }
30444a75411Sfabio.estevam@freescale.com
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)3059d1a50a2SUwe Kleine-König static void imx_uart_ucrs_restore(struct imx_port *sport,
30644a75411Sfabio.estevam@freescale.com struct imx_port_ucrs *ucr)
30744a75411Sfabio.estevam@freescale.com {
30844a75411Sfabio.estevam@freescale.com /* restore control registers */
30927c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr1, UCR1);
31027c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr2, UCR2);
31127c84426SUwe Kleine-König imx_uart_writel(sport, ucr->ucr3, UCR3);
31244a75411Sfabio.estevam@freescale.com }
313e8bfa760SFabio Estevam #endif
31444a75411Sfabio.estevam@freescale.com
3154e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)3169d1a50a2SUwe Kleine-König static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
31758362d5bSUwe Kleine-König {
318bc2be239SFabio Estevam *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
31958362d5bSUwe Kleine-König
3207c7f9bc9SLukas Wunner mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
32158362d5bSUwe Kleine-König }
32258362d5bSUwe Kleine-König
3234e828c3eSSergey Organov /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)3249d1a50a2SUwe Kleine-König static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
32558362d5bSUwe Kleine-König {
326bc2be239SFabio Estevam *ucr2 &= ~UCR2_CTSC;
327bc2be239SFabio Estevam *ucr2 |= UCR2_CTS;
32858362d5bSUwe Kleine-König
3297c7f9bc9SLukas Wunner mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
33058362d5bSUwe Kleine-König }
33158362d5bSUwe Kleine-König
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)332bd78ecd6SAhmad Fatoum static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
333bd78ecd6SAhmad Fatoum {
334f751ae1cSJiri Slaby hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
335bd78ecd6SAhmad Fatoum }
336bd78ecd6SAhmad Fatoum
3376aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)338d45fb2e4SSergey Organov static void imx_uart_soft_reset(struct imx_port *sport)
339d45fb2e4SSergey Organov {
340d45fb2e4SSergey Organov int i = 10;
341d45fb2e4SSergey Organov u32 ucr2, ubir, ubmr, uts;
342d45fb2e4SSergey Organov
343d45fb2e4SSergey Organov /*
344d45fb2e4SSergey Organov * According to the Reference Manual description of the UART SRST bit:
345d45fb2e4SSergey Organov *
346d45fb2e4SSergey Organov * "Reset the transmit and receive state machines,
347d45fb2e4SSergey Organov * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
348d45fb2e4SSergey Organov * and UTS[6-3]".
349d45fb2e4SSergey Organov *
350d45fb2e4SSergey Organov * We don't need to restore the old values from USR1, USR2, URXD and
351d45fb2e4SSergey Organov * UTXD. UBRC is read only, so only save/restore the other three
352d45fb2e4SSergey Organov * registers.
353d45fb2e4SSergey Organov */
354d45fb2e4SSergey Organov ubir = imx_uart_readl(sport, UBIR);
355d45fb2e4SSergey Organov ubmr = imx_uart_readl(sport, UBMR);
356d45fb2e4SSergey Organov uts = imx_uart_readl(sport, IMX21_UTS);
357d45fb2e4SSergey Organov
358d45fb2e4SSergey Organov ucr2 = imx_uart_readl(sport, UCR2);
359d45fb2e4SSergey Organov imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
360d45fb2e4SSergey Organov
361d45fb2e4SSergey Organov while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
362d45fb2e4SSergey Organov udelay(1);
363d45fb2e4SSergey Organov
364d45fb2e4SSergey Organov /* Restore the registers */
365d45fb2e4SSergey Organov imx_uart_writel(sport, ubir, UBIR);
366d45fb2e4SSergey Organov imx_uart_writel(sport, ubmr, UBMR);
367d45fb2e4SSergey Organov imx_uart_writel(sport, uts, IMX21_UTS);
368496a4471SSergey Organov
369496a4471SSergey Organov sport->idle_counter = 0;
370d45fb2e4SSergey Organov }
371d45fb2e4SSergey Organov
imx_uart_disable_loopback_rs485(struct imx_port * sport)372639949a7SMartin Fuzzey static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
373639949a7SMartin Fuzzey {
374639949a7SMartin Fuzzey unsigned int uts;
375639949a7SMartin Fuzzey
376639949a7SMartin Fuzzey /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
377639949a7SMartin Fuzzey uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
378639949a7SMartin Fuzzey uts &= ~UTS_LOOP;
379639949a7SMartin Fuzzey imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
380639949a7SMartin Fuzzey }
381639949a7SMartin Fuzzey
382d45fb2e4SSergey Organov /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)3839d1a50a2SUwe Kleine-König static void imx_uart_start_rx(struct uart_port *port)
38476821e22SUwe Kleine-König {
38576821e22SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port;
38676821e22SUwe Kleine-König unsigned int ucr1, ucr2;
38776821e22SUwe Kleine-König
38876821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
38976821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
39076821e22SUwe Kleine-König
39176821e22SUwe Kleine-König ucr2 |= UCR2_RXEN;
39276821e22SUwe Kleine-König
39376821e22SUwe Kleine-König if (sport->dma_is_enabled) {
39476821e22SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
39576821e22SUwe Kleine-König } else {
39676821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN;
39781ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN;
39876821e22SUwe Kleine-König }
39976821e22SUwe Kleine-König
40076821e22SUwe Kleine-König /* Write UCR2 first as it includes RXEN */
40176821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
40276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
403639949a7SMartin Fuzzey imx_uart_disable_loopback_rs485(sport);
40476821e22SUwe Kleine-König }
40576821e22SUwe Kleine-König
40676821e22SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)4079d1a50a2SUwe Kleine-König static void imx_uart_stop_tx(struct uart_port *port)
408ab4382d2SGreg Kroah-Hartman {
409ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
410cb1a6092SUwe Kleine-König u32 ucr1, ucr4, usr2;
411cb1a6092SUwe Kleine-König
412cb1a6092SUwe Kleine-König if (sport->tx_state == OFF)
413cb1a6092SUwe Kleine-König return;
414ab4382d2SGreg Kroah-Hartman
4159ce4f8f3SGreg Kroah-Hartman /*
4169ce4f8f3SGreg Kroah-Hartman * We are maybe in the SMP context, so if the DMA TX thread is running
4179ce4f8f3SGreg Kroah-Hartman * on other cpu, we have to wait for it to finish.
4189ce4f8f3SGreg Kroah-Hartman */
419686351f3SUwe Kleine-König if (sport->dma_is_txing)
4209ce4f8f3SGreg Kroah-Hartman return;
421b4cdc8f6SHuang Shijie
4224444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
423c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
42417b8f2a3SUwe Kleine-König
425763cd687SPaul Geurts ucr4 = imx_uart_readl(sport, UCR4);
426cb1a6092SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2);
427763cd687SPaul Geurts if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
428cb1a6092SUwe Kleine-König /* The shifter is still busy, so retry once TC triggers */
429cb1a6092SUwe Kleine-König return;
430cb1a6092SUwe Kleine-König }
431cb1a6092SUwe Kleine-König
432cb1a6092SUwe Kleine-König ucr4 &= ~UCR4_TCEN;
433cb1a6092SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4);
434cb1a6092SUwe Kleine-König
435cb1a6092SUwe Kleine-König /* in rs485 mode disable transmitter */
436cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) {
437cb1a6092SUwe Kleine-König if (sport->tx_state == SEND) {
438cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_SEND;
439582e9a24SHarald Seiler
440582e9a24SHarald Seiler if (port->rs485.delay_rts_after_send > 0) {
441bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_stop_tx,
442bd78ecd6SAhmad Fatoum port->rs485.delay_rts_after_send);
443bd78ecd6SAhmad Fatoum return;
444cb1a6092SUwe Kleine-König }
445cb1a6092SUwe Kleine-König
446582e9a24SHarald Seiler /* continue without any delay */
447582e9a24SHarald Seiler }
448582e9a24SHarald Seiler
449cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS ||
450bd78ecd6SAhmad Fatoum sport->tx_state == WAIT_AFTER_SEND) {
451cb1a6092SUwe Kleine-König u32 ucr2;
452cb1a6092SUwe Kleine-König
453bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_start_tx);
454cb1a6092SUwe Kleine-König
455cb1a6092SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
45617b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
4579d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2);
4581a613626SFabio Estevam else
4599d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2);
4604444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
46117b8f2a3SUwe Kleine-König
462ca530cfaSChristoph Niedermaier if (!port->rs485_rx_during_tx_gpio)
4639d1a50a2SUwe Kleine-König imx_uart_start_rx(port);
46476821e22SUwe Kleine-König
465cb1a6092SUwe Kleine-König sport->tx_state = OFF;
466cb1a6092SUwe Kleine-König }
467cb1a6092SUwe Kleine-König } else {
468cb1a6092SUwe Kleine-König sport->tx_state = OFF;
46917b8f2a3SUwe Kleine-König }
470ab4382d2SGreg Kroah-Hartman }
471ab4382d2SGreg Kroah-Hartman
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)47224b5eff4SRickard x Andersson static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
473ab4382d2SGreg Kroah-Hartman {
474ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
47579d0224fSMarek Vasut u32 ucr1, ucr2, ucr4, uts;
476ab4382d2SGreg Kroah-Hartman
4774444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
47876821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
479028e0838SFugang Duan ucr4 = imx_uart_readl(sport, UCR4);
48076821e22SUwe Kleine-König
48176821e22SUwe Kleine-König if (sport->dma_is_enabled) {
48276821e22SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
48376821e22SUwe Kleine-König } else {
48476821e22SUwe Kleine-König ucr1 &= ~UCR1_RRDYEN;
48581ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN;
486028e0838SFugang Duan ucr4 &= ~UCR4_OREN;
48776821e22SUwe Kleine-König }
48876821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
489028e0838SFugang Duan imx_uart_writel(sport, ucr4, UCR4);
49076821e22SUwe Kleine-König
49179d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
49279d0224fSMarek Vasut if (port->rs485.flags & SER_RS485_ENABLED &&
49379d0224fSMarek Vasut port->rs485.flags & SER_RS485_RTS_ON_SEND &&
49424b5eff4SRickard x Andersson sport->have_rtscts && !sport->have_rtsgpio && loopback) {
49579d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
49679d0224fSMarek Vasut uts |= UTS_LOOP;
49779d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
49879d0224fSMarek Vasut ucr2 |= UCR2_RXEN;
49979d0224fSMarek Vasut } else {
50076821e22SUwe Kleine-König ucr2 &= ~UCR2_RXEN;
50179d0224fSMarek Vasut }
50279d0224fSMarek Vasut
50376821e22SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
504ab4382d2SGreg Kroah-Hartman }
505ab4382d2SGreg Kroah-Hartman
5066aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)50724b5eff4SRickard x Andersson static void imx_uart_stop_rx(struct uart_port *port)
50824b5eff4SRickard x Andersson {
50924b5eff4SRickard x Andersson /*
51024b5eff4SRickard x Andersson * Stop RX and enable loopback in order to make sure RS485 bus
51124b5eff4SRickard x Andersson * is not blocked. Se comment in imx_uart_probe().
51224b5eff4SRickard x Andersson */
51324b5eff4SRickard x Andersson imx_uart_stop_rx_with_loopback_ctrl(port, true);
51424b5eff4SRickard x Andersson }
51524b5eff4SRickard x Andersson
51624b5eff4SRickard x Andersson /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)5179d1a50a2SUwe Kleine-König static void imx_uart_enable_ms(struct uart_port *port)
518ab4382d2SGreg Kroah-Hartman {
519ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
520ab4382d2SGreg Kroah-Hartman
521ab4382d2SGreg Kroah-Hartman mod_timer(&sport->timer, jiffies);
52258362d5bSUwe Kleine-König
52358362d5bSUwe Kleine-König mctrl_gpio_enable_ms(sport->gpios);
524ab4382d2SGreg Kroah-Hartman }
525ab4382d2SGreg Kroah-Hartman
5269d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport);
5276aed2a88SUwe Kleine-König
5286aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)5299d1a50a2SUwe Kleine-König static inline void imx_uart_transmit_buffer(struct imx_port *sport)
530ab4382d2SGreg Kroah-Hartman {
531ab4382d2SGreg Kroah-Hartman struct circ_buf *xmit = &sport->port.state->xmit;
532ab4382d2SGreg Kroah-Hartman
5335e42e9a3SPeter Hurley if (sport->port.x_char) {
5345e42e9a3SPeter Hurley /* Send next char */
53527c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.x_char, URTX0);
5367e2fb5aaSJiada Wang sport->port.icount.tx++;
5377e2fb5aaSJiada Wang sport->port.x_char = 0;
5385e42e9a3SPeter Hurley return;
5395e42e9a3SPeter Hurley }
5405e42e9a3SPeter Hurley
5415e42e9a3SPeter Hurley if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
5429d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port);
5435e42e9a3SPeter Hurley return;
5445e42e9a3SPeter Hurley }
5455e42e9a3SPeter Hurley
54691a1a909SJiada Wang if (sport->dma_is_enabled) {
5474444dcf1SUwe Kleine-König u32 ucr1;
54891a1a909SJiada Wang /*
54991a1a909SJiada Wang * We've just sent a X-char Ensure the TX DMA is enabled
55091a1a909SJiada Wang * and the TX IRQ is disabled.
55191a1a909SJiada Wang **/
5524444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
553c514a6f8SSergey Organov ucr1 &= ~UCR1_TRDYEN;
55491a1a909SJiada Wang if (sport->dma_is_txing) {
5554444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN;
5564444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
55791a1a909SJiada Wang } else {
5584444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
5599d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport);
56091a1a909SJiada Wang }
56191a1a909SJiada Wang
5625aabd3b0SIan Jamison return;
5630c549223SUwe Kleine-König }
5645aabd3b0SIan Jamison
5655aabd3b0SIan Jamison while (!uart_circ_empty(xmit) &&
5669d1a50a2SUwe Kleine-König !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
567ab4382d2SGreg Kroah-Hartman /* send xmit->buf[xmit->tail]
568ab4382d2SGreg Kroah-Hartman * out the port here */
56927c84426SUwe Kleine-König imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
57026e8f1d9SIlpo Järvinen uart_xmit_advance(&sport->port, 1);
571ab4382d2SGreg Kroah-Hartman }
572ab4382d2SGreg Kroah-Hartman
573ab4382d2SGreg Kroah-Hartman if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
574ab4382d2SGreg Kroah-Hartman uart_write_wakeup(&sport->port);
575ab4382d2SGreg Kroah-Hartman
576ab4382d2SGreg Kroah-Hartman if (uart_circ_empty(xmit))
5779d1a50a2SUwe Kleine-König imx_uart_stop_tx(&sport->port);
578ab4382d2SGreg Kroah-Hartman }
579ab4382d2SGreg Kroah-Hartman
imx_uart_dma_tx_callback(void * data)5809d1a50a2SUwe Kleine-König static void imx_uart_dma_tx_callback(void *data)
581b4cdc8f6SHuang Shijie {
582b4cdc8f6SHuang Shijie struct imx_port *sport = data;
583b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->tx_sgl[0];
584b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit;
585b4cdc8f6SHuang Shijie unsigned long flags;
5864444dcf1SUwe Kleine-König u32 ucr1;
587b4cdc8f6SHuang Shijie
58842f752b3SDirk Behme spin_lock_irqsave(&sport->port.lock, flags);
58942f752b3SDirk Behme
590b4cdc8f6SHuang Shijie dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
591b4cdc8f6SHuang Shijie
5924444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
5934444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN;
5944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
595a2c718ceSDirk Behme
59626e8f1d9SIlpo Järvinen uart_xmit_advance(&sport->port, sport->tx_bytes);
59742f752b3SDirk Behme
59842f752b3SDirk Behme dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
59942f752b3SDirk Behme
600b4cdc8f6SHuang Shijie sport->dma_is_txing = 0;
601b4cdc8f6SHuang Shijie
602d64b8607SJiada Wang if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
603b4cdc8f6SHuang Shijie uart_write_wakeup(&sport->port);
6049ce4f8f3SGreg Kroah-Hartman
6050bbc9b81SJiada Wang if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
6069d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport);
60718665414SUwe Kleine-König else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
60818665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4);
60918665414SUwe Kleine-König ucr4 |= UCR4_TCEN;
61018665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4);
61118665414SUwe Kleine-König }
61264432a85SUwe Kleine-König
6130bbc9b81SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags);
614b4cdc8f6SHuang Shijie }
615b4cdc8f6SHuang Shijie
6166aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)6179d1a50a2SUwe Kleine-König static void imx_uart_dma_tx(struct imx_port *sport)
618b4cdc8f6SHuang Shijie {
619b4cdc8f6SHuang Shijie struct circ_buf *xmit = &sport->port.state->xmit;
620b4cdc8f6SHuang Shijie struct scatterlist *sgl = sport->tx_sgl;
621b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc;
622b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_tx;
623b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev;
62418665414SUwe Kleine-König u32 ucr1, ucr4;
625b4cdc8f6SHuang Shijie int ret;
626b4cdc8f6SHuang Shijie
62742f752b3SDirk Behme if (sport->dma_is_txing)
628b4cdc8f6SHuang Shijie return;
629b4cdc8f6SHuang Shijie
63018665414SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4);
63118665414SUwe Kleine-König ucr4 &= ~UCR4_TCEN;
63218665414SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4);
63318665414SUwe Kleine-König
634b4cdc8f6SHuang Shijie sport->tx_bytes = uart_circ_chars_pending(xmit);
635b4cdc8f6SHuang Shijie
636f7670783SFugang Duan if (xmit->tail < xmit->head || xmit->head == 0) {
6377942f857SDirk Behme sport->dma_tx_nents = 1;
6387942f857SDirk Behme sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
6397942f857SDirk Behme } else {
640b4cdc8f6SHuang Shijie sport->dma_tx_nents = 2;
641b4cdc8f6SHuang Shijie sg_init_table(sgl, 2);
642b4cdc8f6SHuang Shijie sg_set_buf(sgl, xmit->buf + xmit->tail,
643b4cdc8f6SHuang Shijie UART_XMIT_SIZE - xmit->tail);
644b4cdc8f6SHuang Shijie sg_set_buf(sgl + 1, xmit->buf, xmit->head);
645b4cdc8f6SHuang Shijie }
646b4cdc8f6SHuang Shijie
647b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
648b4cdc8f6SHuang Shijie if (ret == 0) {
649b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for TX.\n");
650b4cdc8f6SHuang Shijie return;
651b4cdc8f6SHuang Shijie }
652596fd8dfSPeng Fan desc = dmaengine_prep_slave_sg(chan, sgl, ret,
653b4cdc8f6SHuang Shijie DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
654b4cdc8f6SHuang Shijie if (!desc) {
65524649821SDirk Behme dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
65624649821SDirk Behme DMA_TO_DEVICE);
657b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the TX slave dma!\n");
658b4cdc8f6SHuang Shijie return;
659b4cdc8f6SHuang Shijie }
6609d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_tx_callback;
661b4cdc8f6SHuang Shijie desc->callback_param = sport;
662b4cdc8f6SHuang Shijie
663b4cdc8f6SHuang Shijie dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
664b4cdc8f6SHuang Shijie uart_circ_chars_pending(xmit));
665a2c718ceSDirk Behme
6664444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
6674444dcf1SUwe Kleine-König ucr1 |= UCR1_TXDMAEN;
6684444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
669a2c718ceSDirk Behme
670b4cdc8f6SHuang Shijie /* fire it */
671b4cdc8f6SHuang Shijie sport->dma_is_txing = 1;
672b4cdc8f6SHuang Shijie dmaengine_submit(desc);
673b4cdc8f6SHuang Shijie dma_async_issue_pending(chan);
674b4cdc8f6SHuang Shijie return;
675b4cdc8f6SHuang Shijie }
676b4cdc8f6SHuang Shijie
6776aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)6789d1a50a2SUwe Kleine-König static void imx_uart_start_tx(struct uart_port *port)
679ab4382d2SGreg Kroah-Hartman {
680ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
6814444dcf1SUwe Kleine-König u32 ucr1;
682ab4382d2SGreg Kroah-Hartman
68348669b69SUwe Kleine-König if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
68448669b69SUwe Kleine-König return;
68548669b69SUwe Kleine-König
686cb1a6092SUwe Kleine-König /*
687cb1a6092SUwe Kleine-König * We cannot simply do nothing here if sport->tx_state == SEND already
688cb1a6092SUwe Kleine-König * because UCR1_TXMPTYEN might already have been cleared in
689cb1a6092SUwe Kleine-König * imx_uart_stop_tx(), but tx_state is still SEND.
690cb1a6092SUwe Kleine-König */
6914444dcf1SUwe Kleine-König
692cb1a6092SUwe Kleine-König if (port->rs485.flags & SER_RS485_ENABLED) {
693cb1a6092SUwe Kleine-König if (sport->tx_state == OFF) {
694cb1a6092SUwe Kleine-König u32 ucr2 = imx_uart_readl(sport, UCR2);
69517b8f2a3SUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
6969d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2);
6971a613626SFabio Estevam else
6989d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2);
6994444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
70017b8f2a3SUwe Kleine-König
70124b5eff4SRickard x Andersson /*
70224b5eff4SRickard x Andersson * Since we are about to transmit we can not stop RX
70324b5eff4SRickard x Andersson * with loopback enabled because that will make our
70424b5eff4SRickard x Andersson * transmitted data being just looped to RX.
70524b5eff4SRickard x Andersson */
706ca530cfaSChristoph Niedermaier if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
707ca530cfaSChristoph Niedermaier !port->rs485_rx_during_tx_gpio)
70824b5eff4SRickard x Andersson imx_uart_stop_rx_with_loopback_ctrl(port, false);
70976821e22SUwe Kleine-König
710cb1a6092SUwe Kleine-König sport->tx_state = WAIT_AFTER_RTS;
711582e9a24SHarald Seiler
712582e9a24SHarald Seiler if (port->rs485.delay_rts_before_send > 0) {
713bd78ecd6SAhmad Fatoum start_hrtimer_ms(&sport->trigger_start_tx,
714bd78ecd6SAhmad Fatoum port->rs485.delay_rts_before_send);
715bd78ecd6SAhmad Fatoum return;
716cb1a6092SUwe Kleine-König }
717cb1a6092SUwe Kleine-König
718582e9a24SHarald Seiler /* continue without any delay */
719582e9a24SHarald Seiler }
720582e9a24SHarald Seiler
721bd78ecd6SAhmad Fatoum if (sport->tx_state == WAIT_AFTER_SEND
722bd78ecd6SAhmad Fatoum || sport->tx_state == WAIT_AFTER_RTS) {
723cb1a6092SUwe Kleine-König
724bd78ecd6SAhmad Fatoum hrtimer_try_to_cancel(&sport->trigger_stop_tx);
725bd78ecd6SAhmad Fatoum
72618665414SUwe Kleine-König /*
727cb1a6092SUwe Kleine-König * Enable transmitter and shifter empty irq only if DMA
728cb1a6092SUwe Kleine-König * is off. In the DMA case this is done in the
729cb1a6092SUwe Kleine-König * tx-callback.
73018665414SUwe Kleine-König */
73118665414SUwe Kleine-König if (!sport->dma_is_enabled) {
73218665414SUwe Kleine-König u32 ucr4 = imx_uart_readl(sport, UCR4);
7334444dcf1SUwe Kleine-König ucr4 |= UCR4_TCEN;
7344444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4);
73517b8f2a3SUwe Kleine-König }
736cb1a6092SUwe Kleine-König
737cb1a6092SUwe Kleine-König sport->tx_state = SEND;
738cb1a6092SUwe Kleine-König }
739cb1a6092SUwe Kleine-König } else {
740cb1a6092SUwe Kleine-König sport->tx_state = SEND;
74118665414SUwe Kleine-König }
74217b8f2a3SUwe Kleine-König
743b4cdc8f6SHuang Shijie if (!sport->dma_is_enabled) {
7444444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
745c514a6f8SSergey Organov imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
746b4cdc8f6SHuang Shijie }
747ab4382d2SGreg Kroah-Hartman
748b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) {
74991a1a909SJiada Wang if (sport->port.x_char) {
75091a1a909SJiada Wang /* We have X-char to send, so enable TX IRQ and
75191a1a909SJiada Wang * disable TX DMA to let TX interrupt to send X-char */
7524444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
7534444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN;
754c514a6f8SSergey Organov ucr1 |= UCR1_TRDYEN;
7554444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
75691a1a909SJiada Wang return;
75791a1a909SJiada Wang }
75891a1a909SJiada Wang
7595e42e9a3SPeter Hurley if (!uart_circ_empty(&port->state->xmit) &&
7605e42e9a3SPeter Hurley !uart_tx_stopped(port))
7619d1a50a2SUwe Kleine-König imx_uart_dma_tx(sport);
762b4cdc8f6SHuang Shijie return;
763b4cdc8f6SHuang Shijie }
764ab4382d2SGreg Kroah-Hartman }
765ab4382d2SGreg Kroah-Hartman
__imx_uart_rtsint(int irq,void * dev_id)766101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
767ab4382d2SGreg Kroah-Hartman {
768ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id;
7694444dcf1SUwe Kleine-König u32 usr1;
770ab4382d2SGreg Kroah-Hartman
77127c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD, USR1);
7724444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
773968d6457SIlpo Järvinen uart_handle_cts_change(&sport->port, usr1);
774ab4382d2SGreg Kroah-Hartman wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
775ab4382d2SGreg Kroah-Hartman
776ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED;
777ab4382d2SGreg Kroah-Hartman }
778ab4382d2SGreg Kroah-Hartman
imx_uart_rtsint(int irq,void * dev_id)779101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
780101aa46bSUwe Kleine-König {
781101aa46bSUwe Kleine-König struct imx_port *sport = dev_id;
782101aa46bSUwe Kleine-König irqreturn_t ret;
783101aa46bSUwe Kleine-König
784101aa46bSUwe Kleine-König spin_lock(&sport->port.lock);
785101aa46bSUwe Kleine-König
786101aa46bSUwe Kleine-König ret = __imx_uart_rtsint(irq, dev_id);
787101aa46bSUwe Kleine-König
788101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock);
789101aa46bSUwe Kleine-König
790101aa46bSUwe Kleine-König return ret;
791101aa46bSUwe Kleine-König }
792101aa46bSUwe Kleine-König
imx_uart_txint(int irq,void * dev_id)7939d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_txint(int irq, void *dev_id)
794ab4382d2SGreg Kroah-Hartman {
795ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id;
796ab4382d2SGreg Kroah-Hartman
797c974991dSjun qian spin_lock(&sport->port.lock);
7989d1a50a2SUwe Kleine-König imx_uart_transmit_buffer(sport);
799c974991dSjun qian spin_unlock(&sport->port.lock);
800ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED;
801ab4382d2SGreg Kroah-Hartman }
802ab4382d2SGreg Kroah-Hartman
803496a4471SSergey Organov /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
804496a4471SSergey Organov * This is to be called from Rx ISRs only when some bytes were actually
805496a4471SSergey Organov * received.
806496a4471SSergey Organov *
807496a4471SSergey Organov * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
808496a4471SSergey Organov * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
809496a4471SSergey Organov * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
810496a4471SSergey Organov * that is terminated by any activity on RxD line, or could be stopped by
811496a4471SSergey Organov * issuing soft reset to the UART (just stop/start of RX does not help). Note
812496a4471SSergey Organov * that what we do here is sending isolated start bit about 2.4 times shorter
813496a4471SSergey Organov * than it is to be on UART configured baud rate.
814496a4471SSergey Organov */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)815496a4471SSergey Organov static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
816496a4471SSergey Organov {
817496a4471SSergey Organov /* To detect hardware 0xff flood we monitor RxD line between RX
818496a4471SSergey Organov * interrupts to isolate "receiving" of char(s) with no activity
819496a4471SSergey Organov * on RxD line, that'd never happen on actual data transfers.
820496a4471SSergey Organov *
821496a4471SSergey Organov * We use USR2_WAKE bit to check for activity on RxD line, but we have a
822496a4471SSergey Organov * race here if we clear USR2_WAKE when receiving of a char is in
823496a4471SSergey Organov * progress, so we might get RX interrupt later with USR2_WAKE bit
824496a4471SSergey Organov * cleared. Note though that as we don't try to clear USR2_WAKE when we
825496a4471SSergey Organov * detected no activity, this race may hide actual activity only once.
826496a4471SSergey Organov *
827496a4471SSergey Organov * Yet another case where receive interrupt may occur without RxD
828496a4471SSergey Organov * activity is expiration of aging timer, so we consider this as well.
829496a4471SSergey Organov *
830496a4471SSergey Organov * We use 'idle_counter' to ensure that we got at least so many RX
831496a4471SSergey Organov * interrupts without any detected activity on RxD line. 2 cases
832496a4471SSergey Organov * described plus 1 to be on the safe side gives us a margin of 3,
833496a4471SSergey Organov * below. In practice I was not able to produce a false positive to
834496a4471SSergey Organov * induce soft reset at regular data transfers even using 1 as the
835496a4471SSergey Organov * margin, so 3 is actually very strong.
836496a4471SSergey Organov *
837496a4471SSergey Organov * We count interrupts, not chars in 'idle-counter' for simplicity.
838496a4471SSergey Organov */
839496a4471SSergey Organov
840496a4471SSergey Organov if (usr2 & USR2_WAKE) {
841496a4471SSergey Organov imx_uart_writel(sport, USR2_WAKE, USR2);
842496a4471SSergey Organov sport->idle_counter = 0;
843496a4471SSergey Organov } else if (++sport->idle_counter > 3) {
844496a4471SSergey Organov dev_warn(sport->port.dev, "RX flood detected: soft reset.");
845496a4471SSergey Organov imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
846496a4471SSergey Organov }
847496a4471SSergey Organov }
848496a4471SSergey Organov
__imx_uart_rxint(int irq,void * dev_id)849101aa46bSUwe Kleine-König static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
850ab4382d2SGreg Kroah-Hartman {
851ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id;
85292a19f9cSJiri Slaby struct tty_port *port = &sport->port.state->port;
8532af4b918SSergey Organov u32 usr2, rx;
8544444dcf1SUwe Kleine-König
855496a4471SSergey Organov /* If we received something, check for 0xff flood */
85653701b6dSSergey Organov usr2 = imx_uart_readl(sport, USR2);
857496a4471SSergey Organov if (usr2 & USR2_RDR)
858496a4471SSergey Organov imx_uart_check_flood(sport, usr2);
859496a4471SSergey Organov
86053701b6dSSergey Organov while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
8612af4b918SSergey Organov unsigned int flg = TTY_NORMAL;
862ab4382d2SGreg Kroah-Hartman sport->port.icount.rx++;
863ab4382d2SGreg Kroah-Hartman
86453701b6dSSergey Organov if (unlikely(rx & URXD_ERR)) {
86553701b6dSSergey Organov if (rx & URXD_BRK) {
86653701b6dSSergey Organov sport->port.icount.brk++;
867ab4382d2SGreg Kroah-Hartman if (uart_handle_break(&sport->port))
868ab4382d2SGreg Kroah-Hartman continue;
869ab4382d2SGreg Kroah-Hartman }
870019dc9eaSHui Wang else if (rx & URXD_PRERR)
871ab4382d2SGreg Kroah-Hartman sport->port.icount.parity++;
872ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR)
873ab4382d2SGreg Kroah-Hartman sport->port.icount.frame++;
874ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN)
875ab4382d2SGreg Kroah-Hartman sport->port.icount.overrun++;
876ab4382d2SGreg Kroah-Hartman
877fbf97170SSergey Organov if (rx & sport->port.ignore_status_mask)
878ab4382d2SGreg Kroah-Hartman continue;
879ab4382d2SGreg Kroah-Hartman
8808d267fd9SEric Nelson rx &= (sport->port.read_status_mask | 0xFF);
881ab4382d2SGreg Kroah-Hartman
882019dc9eaSHui Wang if (rx & URXD_BRK)
883019dc9eaSHui Wang flg = TTY_BREAK;
884019dc9eaSHui Wang else if (rx & URXD_PRERR)
885ab4382d2SGreg Kroah-Hartman flg = TTY_PARITY;
886ab4382d2SGreg Kroah-Hartman else if (rx & URXD_FRMERR)
887ab4382d2SGreg Kroah-Hartman flg = TTY_FRAME;
888ab4382d2SGreg Kroah-Hartman if (rx & URXD_OVRRUN)
889ab4382d2SGreg Kroah-Hartman flg = TTY_OVERRUN;
890ab4382d2SGreg Kroah-Hartman
891ab4382d2SGreg Kroah-Hartman sport->port.sysrq = 0;
892e1c6a7e5SSergey Organov } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
893e1c6a7e5SSergey Organov continue;
894ab4382d2SGreg Kroah-Hartman }
895ab4382d2SGreg Kroah-Hartman
89655d8693aSJiada Wang if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
897fbf97170SSergey Organov continue;
89855d8693aSJiada Wang
8999b289932SManfred Schlaegl if (tty_insert_flip_char(port, rx, flg) == 0)
9009b289932SManfred Schlaegl sport->port.icount.buf_overrun++;
901ab4382d2SGreg Kroah-Hartman }
902ab4382d2SGreg Kroah-Hartman
9032e124b4aSJiri Slaby tty_flip_buffer_push(port);
904101aa46bSUwe Kleine-König
905ab4382d2SGreg Kroah-Hartman return IRQ_HANDLED;
906ab4382d2SGreg Kroah-Hartman }
907ab4382d2SGreg Kroah-Hartman
imx_uart_rxint(int irq,void * dev_id)908101aa46bSUwe Kleine-König static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
909101aa46bSUwe Kleine-König {
910101aa46bSUwe Kleine-König struct imx_port *sport = dev_id;
911101aa46bSUwe Kleine-König irqreturn_t ret;
912101aa46bSUwe Kleine-König
913101aa46bSUwe Kleine-König spin_lock(&sport->port.lock);
914101aa46bSUwe Kleine-König
915101aa46bSUwe Kleine-König ret = __imx_uart_rxint(irq, dev_id);
916101aa46bSUwe Kleine-König
917101aa46bSUwe Kleine-König spin_unlock(&sport->port.lock);
918101aa46bSUwe Kleine-König
919101aa46bSUwe Kleine-König return ret;
920101aa46bSUwe Kleine-König }
921101aa46bSUwe Kleine-König
9229d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport);
923b4cdc8f6SHuang Shijie
92466f95884SUwe Kleine-König /*
92566f95884SUwe Kleine-König * We have a modem side uart, so the meanings of RTS and CTS are inverted.
92666f95884SUwe Kleine-König */
imx_uart_get_hwmctrl(struct imx_port * sport)9279d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
92866f95884SUwe Kleine-König {
92966f95884SUwe Kleine-König unsigned int tmp = TIOCM_DSR;
93027c84426SUwe Kleine-König unsigned usr1 = imx_uart_readl(sport, USR1);
93127c84426SUwe Kleine-König unsigned usr2 = imx_uart_readl(sport, USR2);
93266f95884SUwe Kleine-König
93366f95884SUwe Kleine-König if (usr1 & USR1_RTSS)
93466f95884SUwe Kleine-König tmp |= TIOCM_CTS;
93566f95884SUwe Kleine-König
93666f95884SUwe Kleine-König /* in DCE mode DCDIN is always 0 */
9374b75f800SSascha Hauer if (!(usr2 & USR2_DCDIN))
93866f95884SUwe Kleine-König tmp |= TIOCM_CAR;
93966f95884SUwe Kleine-König
94066f95884SUwe Kleine-König if (sport->dte_mode)
94127c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
94266f95884SUwe Kleine-König tmp |= TIOCM_RI;
94366f95884SUwe Kleine-König
94466f95884SUwe Kleine-König return tmp;
94566f95884SUwe Kleine-König }
94666f95884SUwe Kleine-König
94766f95884SUwe Kleine-König /*
94866f95884SUwe Kleine-König * Handle any change of modem status signal since we were last called.
94966f95884SUwe Kleine-König */
imx_uart_mctrl_check(struct imx_port * sport)9509d1a50a2SUwe Kleine-König static void imx_uart_mctrl_check(struct imx_port *sport)
95166f95884SUwe Kleine-König {
95266f95884SUwe Kleine-König unsigned int status, changed;
95366f95884SUwe Kleine-König
9549d1a50a2SUwe Kleine-König status = imx_uart_get_hwmctrl(sport);
95566f95884SUwe Kleine-König changed = status ^ sport->old_status;
95666f95884SUwe Kleine-König
95766f95884SUwe Kleine-König if (changed == 0)
95866f95884SUwe Kleine-König return;
95966f95884SUwe Kleine-König
96066f95884SUwe Kleine-König sport->old_status = status;
96166f95884SUwe Kleine-König
96266f95884SUwe Kleine-König if (changed & TIOCM_RI && status & TIOCM_RI)
96366f95884SUwe Kleine-König sport->port.icount.rng++;
96466f95884SUwe Kleine-König if (changed & TIOCM_DSR)
96566f95884SUwe Kleine-König sport->port.icount.dsr++;
96666f95884SUwe Kleine-König if (changed & TIOCM_CAR)
96766f95884SUwe Kleine-König uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
96866f95884SUwe Kleine-König if (changed & TIOCM_CTS)
96966f95884SUwe Kleine-König uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
97066f95884SUwe Kleine-König
97166f95884SUwe Kleine-König wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
97266f95884SUwe Kleine-König }
97366f95884SUwe Kleine-König
imx_uart_int(int irq,void * dev_id)9749d1a50a2SUwe Kleine-König static irqreturn_t imx_uart_int(int irq, void *dev_id)
975ab4382d2SGreg Kroah-Hartman {
976ab4382d2SGreg Kroah-Hartman struct imx_port *sport = dev_id;
97743776896SUwe Kleine-König unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
9784d845a62SUwe Kleine-König irqreturn_t ret = IRQ_NONE;
979ab4382d2SGreg Kroah-Hartman
9809baedb7bSJohan Hovold spin_lock(&sport->port.lock);
981101aa46bSUwe Kleine-König
98227c84426SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1);
98327c84426SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2);
98427c84426SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
98527c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
98627c84426SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3);
98727c84426SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4);
988ab4382d2SGreg Kroah-Hartman
98943776896SUwe Kleine-König /*
99043776896SUwe Kleine-König * Even if a condition is true that can trigger an irq only handle it if
99143776896SUwe Kleine-König * the respective irq source is enabled. This prevents some undesired
99243776896SUwe Kleine-König * actions, for example if a character that sits in the RX FIFO and that
99343776896SUwe Kleine-König * should be fetched via DMA is tried to be fetched using PIO. Or the
99443776896SUwe Kleine-König * receiver is currently off and so reading from URXD0 results in an
99543776896SUwe Kleine-König * exception. So just mask the (raw) status bits for disabled irqs.
99643776896SUwe Kleine-König */
99743776896SUwe Kleine-König if ((ucr1 & UCR1_RRDYEN) == 0)
99843776896SUwe Kleine-König usr1 &= ~USR1_RRDY;
99943776896SUwe Kleine-König if ((ucr2 & UCR2_ATEN) == 0)
100043776896SUwe Kleine-König usr1 &= ~USR1_AGTIM;
1001c514a6f8SSergey Organov if ((ucr1 & UCR1_TRDYEN) == 0)
100243776896SUwe Kleine-König usr1 &= ~USR1_TRDY;
100343776896SUwe Kleine-König if ((ucr4 & UCR4_TCEN) == 0)
100443776896SUwe Kleine-König usr2 &= ~USR2_TXDC;
100543776896SUwe Kleine-König if ((ucr3 & UCR3_DTRDEN) == 0)
100643776896SUwe Kleine-König usr1 &= ~USR1_DTRD;
100743776896SUwe Kleine-König if ((ucr1 & UCR1_RTSDEN) == 0)
100843776896SUwe Kleine-König usr1 &= ~USR1_RTSD;
100943776896SUwe Kleine-König if ((ucr3 & UCR3_AWAKEN) == 0)
101043776896SUwe Kleine-König usr1 &= ~USR1_AWAKE;
101143776896SUwe Kleine-König if ((ucr4 & UCR4_OREN) == 0)
101243776896SUwe Kleine-König usr2 &= ~USR2_ORE;
101343776896SUwe Kleine-König
101443776896SUwe Kleine-König if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1015d1d996afSMatthias Schiffer imx_uart_writel(sport, USR1_AGTIM, USR1);
1016d1d996afSMatthias Schiffer
1017101aa46bSUwe Kleine-König __imx_uart_rxint(irq, dev_id);
10184d845a62SUwe Kleine-König ret = IRQ_HANDLED;
1019b4cdc8f6SHuang Shijie }
1020ab4382d2SGreg Kroah-Hartman
102143776896SUwe Kleine-König if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1022101aa46bSUwe Kleine-König imx_uart_transmit_buffer(sport);
10234d845a62SUwe Kleine-König ret = IRQ_HANDLED;
10244d845a62SUwe Kleine-König }
1025ab4382d2SGreg Kroah-Hartman
10260399fd61SUwe Kleine-König if (usr1 & USR1_DTRD) {
102727c84426SUwe Kleine-König imx_uart_writel(sport, USR1_DTRD, USR1);
102827e16501SUwe Kleine-König
10299d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport);
103027e16501SUwe Kleine-König
103127e16501SUwe Kleine-König ret = IRQ_HANDLED;
103227e16501SUwe Kleine-König }
103327e16501SUwe Kleine-König
10340399fd61SUwe Kleine-König if (usr1 & USR1_RTSD) {
1035101aa46bSUwe Kleine-König __imx_uart_rtsint(irq, dev_id);
10364d845a62SUwe Kleine-König ret = IRQ_HANDLED;
10374d845a62SUwe Kleine-König }
1038ab4382d2SGreg Kroah-Hartman
10390399fd61SUwe Kleine-König if (usr1 & USR1_AWAKE) {
104027c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1);
10414d845a62SUwe Kleine-König ret = IRQ_HANDLED;
10424d845a62SUwe Kleine-König }
1043db1a9b55SFabio Estevam
10440399fd61SUwe Kleine-König if (usr2 & USR2_ORE) {
1045f1f836e4SAlexander Stein sport->port.icount.overrun++;
104627c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2);
10474d845a62SUwe Kleine-König ret = IRQ_HANDLED;
1048f1f836e4SAlexander Stein }
1049f1f836e4SAlexander Stein
10509baedb7bSJohan Hovold spin_unlock(&sport->port.lock);
1051101aa46bSUwe Kleine-König
10524d845a62SUwe Kleine-König return ret;
1053ab4382d2SGreg Kroah-Hartman }
1054ab4382d2SGreg Kroah-Hartman
1055ab4382d2SGreg Kroah-Hartman /*
1056ab4382d2SGreg Kroah-Hartman * Return TIOCSER_TEMT when transmitter is not busy.
1057ab4382d2SGreg Kroah-Hartman */
imx_uart_tx_empty(struct uart_port * port)10589d1a50a2SUwe Kleine-König static unsigned int imx_uart_tx_empty(struct uart_port *port)
1059ab4382d2SGreg Kroah-Hartman {
1060ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
10611ce43e58SHuang Shijie unsigned int ret;
1062ab4382d2SGreg Kroah-Hartman
106327c84426SUwe Kleine-König ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
10641ce43e58SHuang Shijie
10651ce43e58SHuang Shijie /* If the TX DMA is working, return 0. */
1066686351f3SUwe Kleine-König if (sport->dma_is_txing)
10671ce43e58SHuang Shijie ret = 0;
10681ce43e58SHuang Shijie
10691ce43e58SHuang Shijie return ret;
1070ab4382d2SGreg Kroah-Hartman }
1071ab4382d2SGreg Kroah-Hartman
10726aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)10739d1a50a2SUwe Kleine-König static unsigned int imx_uart_get_mctrl(struct uart_port *port)
107458362d5bSUwe Kleine-König {
107558362d5bSUwe Kleine-König struct imx_port *sport = (struct imx_port *)port;
10769d1a50a2SUwe Kleine-König unsigned int ret = imx_uart_get_hwmctrl(sport);
107758362d5bSUwe Kleine-König
107858362d5bSUwe Kleine-König mctrl_gpio_get(sport->gpios, &ret);
107958362d5bSUwe Kleine-König
108058362d5bSUwe Kleine-König return ret;
108158362d5bSUwe Kleine-König }
108258362d5bSUwe Kleine-König
10836aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)10849d1a50a2SUwe Kleine-König static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1085ab4382d2SGreg Kroah-Hartman {
1086ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
10874444dcf1SUwe Kleine-König u32 ucr3, uts;
1088ab4382d2SGreg Kroah-Hartman
108917b8f2a3SUwe Kleine-König if (!(port->rs485.flags & SER_RS485_ENABLED)) {
10904444dcf1SUwe Kleine-König u32 ucr2;
10914444dcf1SUwe Kleine-König
1092197540dcSSergey Organov /*
1093197540dcSSergey Organov * Turn off autoRTS if RTS is lowered and restore autoRTS
1094197540dcSSergey Organov * setting if RTS is raised.
1095197540dcSSergey Organov */
10964444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
10974444dcf1SUwe Kleine-König ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1098197540dcSSergey Organov if (mctrl & TIOCM_RTS) {
1099197540dcSSergey Organov ucr2 |= UCR2_CTS;
1100197540dcSSergey Organov /*
1101197540dcSSergey Organov * UCR2_IRTS is unset if and only if the port is
1102197540dcSSergey Organov * configured for CRTSCTS, so we use inverted UCR2_IRTS
1103197540dcSSergey Organov * to get the state to restore to.
1104197540dcSSergey Organov */
1105197540dcSSergey Organov if (!(ucr2 & UCR2_IRTS))
1106197540dcSSergey Organov ucr2 |= UCR2_CTSC;
1107197540dcSSergey Organov }
11084444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
110917b8f2a3SUwe Kleine-König }
11106b471a98SHuang Shijie
11114444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
111290ebc483SUwe Kleine-König if (!(mctrl & TIOCM_DTR))
11134444dcf1SUwe Kleine-König ucr3 |= UCR3_DSR;
11144444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3);
111590ebc483SUwe Kleine-König
11169d1a50a2SUwe Kleine-König uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
11176b471a98SHuang Shijie if (mctrl & TIOCM_LOOP)
11184444dcf1SUwe Kleine-König uts |= UTS_LOOP;
11199d1a50a2SUwe Kleine-König imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
112058362d5bSUwe Kleine-König
112158362d5bSUwe Kleine-König mctrl_gpio_set(sport->gpios, mctrl);
1122ab4382d2SGreg Kroah-Hartman }
1123ab4382d2SGreg Kroah-Hartman
1124ab4382d2SGreg Kroah-Hartman /*
1125ab4382d2SGreg Kroah-Hartman * Interrupts always disabled.
1126ab4382d2SGreg Kroah-Hartman */
imx_uart_break_ctl(struct uart_port * port,int break_state)11279d1a50a2SUwe Kleine-König static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1128ab4382d2SGreg Kroah-Hartman {
1129ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
11304444dcf1SUwe Kleine-König unsigned long flags;
11314444dcf1SUwe Kleine-König u32 ucr1;
1132ab4382d2SGreg Kroah-Hartman
1133ab4382d2SGreg Kroah-Hartman spin_lock_irqsave(&sport->port.lock, flags);
1134ab4382d2SGreg Kroah-Hartman
11354444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1136ab4382d2SGreg Kroah-Hartman
1137ab4382d2SGreg Kroah-Hartman if (break_state != 0)
11384444dcf1SUwe Kleine-König ucr1 |= UCR1_SNDBRK;
1139ab4382d2SGreg Kroah-Hartman
11404444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
1141ab4382d2SGreg Kroah-Hartman
1142ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags);
1143ab4382d2SGreg Kroah-Hartman }
1144ab4382d2SGreg Kroah-Hartman
1145cc568849SUwe Kleine-König /*
1146cc568849SUwe Kleine-König * This is our per-port timeout handler, for checking the
1147cc568849SUwe Kleine-König * modem status signals.
1148cc568849SUwe Kleine-König */
imx_uart_timeout(struct timer_list * t)11499d1a50a2SUwe Kleine-König static void imx_uart_timeout(struct timer_list *t)
1150cc568849SUwe Kleine-König {
1151e99e88a9SKees Cook struct imx_port *sport = from_timer(sport, t, timer);
1152cc568849SUwe Kleine-König unsigned long flags;
1153cc568849SUwe Kleine-König
1154cc568849SUwe Kleine-König if (sport->port.state) {
1155cc568849SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags);
11569d1a50a2SUwe Kleine-König imx_uart_mctrl_check(sport);
1157cc568849SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags);
1158cc568849SUwe Kleine-König
1159cc568849SUwe Kleine-König mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1160cc568849SUwe Kleine-König }
1161cc568849SUwe Kleine-König }
1162cc568849SUwe Kleine-König
1163b4cdc8f6SHuang Shijie /*
1164905c0decSLucas Stach * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1165b4cdc8f6SHuang Shijie * [1] the RX DMA buffer is full.
1166905c0decSLucas Stach * [2] the aging timer expires
1167b4cdc8f6SHuang Shijie *
1168905c0decSLucas Stach * Condition [2] is triggered when a character has been sitting in the FIFO
1169905c0decSLucas Stach * for at least 8 byte durations.
1170b4cdc8f6SHuang Shijie */
imx_uart_dma_rx_callback(void * data)11719d1a50a2SUwe Kleine-König static void imx_uart_dma_rx_callback(void *data)
1172b4cdc8f6SHuang Shijie {
1173b4cdc8f6SHuang Shijie struct imx_port *sport = data;
1174b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx;
1175b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl;
11767cb92fd2SHuang Shijie struct tty_port *port = &sport->port.state->port;
1177b4cdc8f6SHuang Shijie struct dma_tx_state state;
11789d297239SNandor Han struct circ_buf *rx_ring = &sport->rx_ring;
1179b4cdc8f6SHuang Shijie enum dma_status status;
11809d297239SNandor Han unsigned int w_bytes = 0;
11819d297239SNandor Han unsigned int r_bytes;
11829d297239SNandor Han unsigned int bd_size;
1183b4cdc8f6SHuang Shijie
1184fb7f1bf8SRobin Gong status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1185392bceedSPhilipp Zabel
11869d297239SNandor Han if (status == DMA_ERROR) {
1187496a4471SSergey Organov spin_lock(&sport->port.lock);
11889d1a50a2SUwe Kleine-König imx_uart_clear_rx_errors(sport);
1189496a4471SSergey Organov spin_unlock(&sport->port.lock);
11909d297239SNandor Han return;
11919d297239SNandor Han }
1192b4cdc8f6SHuang Shijie
1193976b39cdSLucas Stach /*
11949d297239SNandor Han * The state-residue variable represents the empty space
11959d297239SNandor Han * relative to the entire buffer. Taking this in consideration
11969d297239SNandor Han * the head is always calculated base on the buffer total
11979d297239SNandor Han * length - DMA transaction residue. The UART script from the
11989d297239SNandor Han * SDMA firmware will jump to the next buffer descriptor,
11999d297239SNandor Han * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
12009d297239SNandor Han * Taking this in consideration the tail is always at the
12019d297239SNandor Han * beginning of the buffer descriptor that contains the head.
1202976b39cdSLucas Stach */
12039d297239SNandor Han
12049d297239SNandor Han /* Calculate the head */
12059d297239SNandor Han rx_ring->head = sg_dma_len(sgl) - state.residue;
12069d297239SNandor Han
12079d297239SNandor Han /* Calculate the tail. */
12089d297239SNandor Han bd_size = sg_dma_len(sgl) / sport->rx_periods;
12099d297239SNandor Han rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
12109d297239SNandor Han
12119d297239SNandor Han if (rx_ring->head <= sg_dma_len(sgl) &&
12129d297239SNandor Han rx_ring->head > rx_ring->tail) {
12139d297239SNandor Han
12149d297239SNandor Han /* Move data from tail to head */
12159d297239SNandor Han r_bytes = rx_ring->head - rx_ring->tail;
12169d297239SNandor Han
1217496a4471SSergey Organov /* If we received something, check for 0xff flood */
1218496a4471SSergey Organov spin_lock(&sport->port.lock);
1219496a4471SSergey Organov imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1220496a4471SSergey Organov spin_unlock(&sport->port.lock);
1221496a4471SSergey Organov
1222496a4471SSergey Organov if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1223496a4471SSergey Organov
12249d297239SNandor Han /* CPU claims ownership of RX DMA buffer */
12259d297239SNandor Han dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
12269d297239SNandor Han DMA_FROM_DEVICE);
12279d297239SNandor Han
12289d297239SNandor Han w_bytes = tty_insert_flip_string(port,
12299d297239SNandor Han sport->rx_buf + rx_ring->tail, r_bytes);
12309d297239SNandor Han
12319d297239SNandor Han /* UART retrieves ownership of RX DMA buffer */
12329d297239SNandor Han dma_sync_sg_for_device(sport->port.dev, sgl, 1,
12339d297239SNandor Han DMA_FROM_DEVICE);
12349d297239SNandor Han
12359d297239SNandor Han if (w_bytes != r_bytes)
12369d297239SNandor Han sport->port.icount.buf_overrun++;
12379d297239SNandor Han
12389d297239SNandor Han sport->port.icount.rx += w_bytes;
1239496a4471SSergey Organov }
12409d297239SNandor Han } else {
12419d297239SNandor Han WARN_ON(rx_ring->head > sg_dma_len(sgl));
12429d297239SNandor Han WARN_ON(rx_ring->head <= rx_ring->tail);
1243ee5e7c10SRobin Gong }
12449d297239SNandor Han
12459d297239SNandor Han if (w_bytes) {
12469d297239SNandor Han tty_flip_buffer_push(port);
12479d297239SNandor Han dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
12489d297239SNandor Han }
12499d297239SNandor Han }
12509d297239SNandor Han
imx_uart_start_rx_dma(struct imx_port * sport)12519d1a50a2SUwe Kleine-König static int imx_uart_start_rx_dma(struct imx_port *sport)
1252b4cdc8f6SHuang Shijie {
1253b4cdc8f6SHuang Shijie struct scatterlist *sgl = &sport->rx_sgl;
1254b4cdc8f6SHuang Shijie struct dma_chan *chan = sport->dma_chan_rx;
1255b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev;
1256b4cdc8f6SHuang Shijie struct dma_async_tx_descriptor *desc;
1257b4cdc8f6SHuang Shijie int ret;
1258b4cdc8f6SHuang Shijie
12599d297239SNandor Han sport->rx_ring.head = 0;
12609d297239SNandor Han sport->rx_ring.tail = 0;
12619d297239SNandor Han
1262db0a196bSFabien Lahoudere sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1263b4cdc8f6SHuang Shijie ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1264b4cdc8f6SHuang Shijie if (ret == 0) {
1265b4cdc8f6SHuang Shijie dev_err(dev, "DMA mapping error for RX.\n");
1266b4cdc8f6SHuang Shijie return -EINVAL;
1267b4cdc8f6SHuang Shijie }
12689d297239SNandor Han
12699d297239SNandor Han desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
12709d297239SNandor Han sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
12719d297239SNandor Han DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
12729d297239SNandor Han
1273b4cdc8f6SHuang Shijie if (!desc) {
127424649821SDirk Behme dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1275b4cdc8f6SHuang Shijie dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1276b4cdc8f6SHuang Shijie return -EINVAL;
1277b4cdc8f6SHuang Shijie }
12789d1a50a2SUwe Kleine-König desc->callback = imx_uart_dma_rx_callback;
1279b4cdc8f6SHuang Shijie desc->callback_param = sport;
1280b4cdc8f6SHuang Shijie
1281b4cdc8f6SHuang Shijie dev_dbg(dev, "RX: prepare for the DMA.\n");
12824139fd76SRomain Perier sport->dma_is_rxing = 1;
12839d297239SNandor Han sport->rx_cookie = dmaengine_submit(desc);
1284b4cdc8f6SHuang Shijie dma_async_issue_pending(chan);
1285b4cdc8f6SHuang Shijie return 0;
1286b4cdc8f6SHuang Shijie }
1287b4cdc8f6SHuang Shijie
imx_uart_clear_rx_errors(struct imx_port * sport)12889d1a50a2SUwe Kleine-König static void imx_uart_clear_rx_errors(struct imx_port *sport)
128941d98b5dSNandor Han {
129045ca673eSTroy Kisky struct tty_port *port = &sport->port.state->port;
12914444dcf1SUwe Kleine-König u32 usr1, usr2;
129241d98b5dSNandor Han
12934444dcf1SUwe Kleine-König usr1 = imx_uart_readl(sport, USR1);
12944444dcf1SUwe Kleine-König usr2 = imx_uart_readl(sport, USR2);
129541d98b5dSNandor Han
12964444dcf1SUwe Kleine-König if (usr2 & USR2_BRCD) {
129741d98b5dSNandor Han sport->port.icount.brk++;
129827c84426SUwe Kleine-König imx_uart_writel(sport, USR2_BRCD, USR2);
129945ca673eSTroy Kisky uart_handle_break(&sport->port);
130045ca673eSTroy Kisky if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
130145ca673eSTroy Kisky sport->port.icount.buf_overrun++;
130245ca673eSTroy Kisky tty_flip_buffer_push(port);
130345ca673eSTroy Kisky } else {
13044444dcf1SUwe Kleine-König if (usr1 & USR1_FRAMERR) {
130541d98b5dSNandor Han sport->port.icount.frame++;
130627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_FRAMERR, USR1);
13074444dcf1SUwe Kleine-König } else if (usr1 & USR1_PARITYERR) {
130841d98b5dSNandor Han sport->port.icount.parity++;
130927c84426SUwe Kleine-König imx_uart_writel(sport, USR1_PARITYERR, USR1);
131041d98b5dSNandor Han }
131145ca673eSTroy Kisky }
131241d98b5dSNandor Han
13134444dcf1SUwe Kleine-König if (usr2 & USR2_ORE) {
131441d98b5dSNandor Han sport->port.icount.overrun++;
131527c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2);
131641d98b5dSNandor Han }
131741d98b5dSNandor Han
1318496a4471SSergey Organov sport->idle_counter = 0;
1319496a4471SSergey Organov
132041d98b5dSNandor Han }
132141d98b5dSNandor Han
1322cc32382dSLucas Stach #define TXTL_DEFAULT 2 /* reset default */
13237a637784STomasz Moń #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1324184bd70bSLucas Stach #define TXTL_DMA 8 /* DMA burst setting */
1325184bd70bSLucas Stach #define RXTL_DMA 9 /* DMA burst setting */
1326cc32382dSLucas Stach
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)13279d1a50a2SUwe Kleine-König static void imx_uart_setup_ufcr(struct imx_port *sport,
1328cc32382dSLucas Stach unsigned char txwl, unsigned char rxwl)
1329cc32382dSLucas Stach {
1330cc32382dSLucas Stach unsigned int val;
1331cc32382dSLucas Stach
1332cc32382dSLucas Stach /* set receiver / transmitter trigger level */
133327c84426SUwe Kleine-König val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1334cc32382dSLucas Stach val |= txwl << UFCR_TXTL_SHF | rxwl;
133527c84426SUwe Kleine-König imx_uart_writel(sport, val, UFCR);
1336cc32382dSLucas Stach }
1337cc32382dSLucas Stach
imx_uart_dma_exit(struct imx_port * sport)1338b4cdc8f6SHuang Shijie static void imx_uart_dma_exit(struct imx_port *sport)
1339b4cdc8f6SHuang Shijie {
1340b4cdc8f6SHuang Shijie if (sport->dma_chan_rx) {
1341e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx);
1342b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_rx);
1343b4cdc8f6SHuang Shijie sport->dma_chan_rx = NULL;
13449d297239SNandor Han sport->rx_cookie = -EINVAL;
1345b4cdc8f6SHuang Shijie kfree(sport->rx_buf);
1346b4cdc8f6SHuang Shijie sport->rx_buf = NULL;
1347b4cdc8f6SHuang Shijie }
1348b4cdc8f6SHuang Shijie
1349b4cdc8f6SHuang Shijie if (sport->dma_chan_tx) {
1350e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx);
1351b4cdc8f6SHuang Shijie dma_release_channel(sport->dma_chan_tx);
1352b4cdc8f6SHuang Shijie sport->dma_chan_tx = NULL;
1353b4cdc8f6SHuang Shijie }
1354b4cdc8f6SHuang Shijie }
1355b4cdc8f6SHuang Shijie
imx_uart_dma_init(struct imx_port * sport)1356b4cdc8f6SHuang Shijie static int imx_uart_dma_init(struct imx_port *sport)
1357b4cdc8f6SHuang Shijie {
1358b09c74aeSHuang Shijie struct dma_slave_config slave_config = {};
1359b4cdc8f6SHuang Shijie struct device *dev = sport->port.dev;
1360b4cdc8f6SHuang Shijie int ret;
1361b4cdc8f6SHuang Shijie
1362b4cdc8f6SHuang Shijie /* Prepare for RX : */
1363b4cdc8f6SHuang Shijie sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1364b4cdc8f6SHuang Shijie if (!sport->dma_chan_rx) {
1365b4cdc8f6SHuang Shijie dev_dbg(dev, "cannot get the DMA channel.\n");
1366b4cdc8f6SHuang Shijie ret = -EINVAL;
1367b4cdc8f6SHuang Shijie goto err;
1368b4cdc8f6SHuang Shijie }
1369b4cdc8f6SHuang Shijie
1370b4cdc8f6SHuang Shijie slave_config.direction = DMA_DEV_TO_MEM;
1371b4cdc8f6SHuang Shijie slave_config.src_addr = sport->port.mapbase + URXD0;
1372b4cdc8f6SHuang Shijie slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1373184bd70bSLucas Stach /* one byte less than the watermark level to enable the aging timer */
1374184bd70bSLucas Stach slave_config.src_maxburst = RXTL_DMA - 1;
1375b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1376b4cdc8f6SHuang Shijie if (ret) {
1377b4cdc8f6SHuang Shijie dev_err(dev, "error in RX dma configuration.\n");
1378b4cdc8f6SHuang Shijie goto err;
1379b4cdc8f6SHuang Shijie }
1380b4cdc8f6SHuang Shijie
1381db0a196bSFabien Lahoudere sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1382db0a196bSFabien Lahoudere sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1383b4cdc8f6SHuang Shijie if (!sport->rx_buf) {
1384b4cdc8f6SHuang Shijie ret = -ENOMEM;
1385b4cdc8f6SHuang Shijie goto err;
1386b4cdc8f6SHuang Shijie }
13879d297239SNandor Han sport->rx_ring.buf = sport->rx_buf;
1388b4cdc8f6SHuang Shijie
1389b4cdc8f6SHuang Shijie /* Prepare for TX : */
1390b4cdc8f6SHuang Shijie sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1391b4cdc8f6SHuang Shijie if (!sport->dma_chan_tx) {
1392b4cdc8f6SHuang Shijie dev_err(dev, "cannot get the TX DMA channel!\n");
1393b4cdc8f6SHuang Shijie ret = -EINVAL;
1394b4cdc8f6SHuang Shijie goto err;
1395b4cdc8f6SHuang Shijie }
1396b4cdc8f6SHuang Shijie
1397b4cdc8f6SHuang Shijie slave_config.direction = DMA_MEM_TO_DEV;
1398b4cdc8f6SHuang Shijie slave_config.dst_addr = sport->port.mapbase + URTX0;
1399b4cdc8f6SHuang Shijie slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1400184bd70bSLucas Stach slave_config.dst_maxburst = TXTL_DMA;
1401b4cdc8f6SHuang Shijie ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1402b4cdc8f6SHuang Shijie if (ret) {
1403b4cdc8f6SHuang Shijie dev_err(dev, "error in TX dma configuration.");
1404b4cdc8f6SHuang Shijie goto err;
1405b4cdc8f6SHuang Shijie }
1406b4cdc8f6SHuang Shijie
1407b4cdc8f6SHuang Shijie return 0;
1408b4cdc8f6SHuang Shijie err:
1409b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport);
1410b4cdc8f6SHuang Shijie return ret;
1411b4cdc8f6SHuang Shijie }
1412b4cdc8f6SHuang Shijie
imx_uart_enable_dma(struct imx_port * sport)14139d1a50a2SUwe Kleine-König static void imx_uart_enable_dma(struct imx_port *sport)
1414b4cdc8f6SHuang Shijie {
14154444dcf1SUwe Kleine-König u32 ucr1;
1416b4cdc8f6SHuang Shijie
14179d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
141802b0abd3SUwe Kleine-König
1419b4cdc8f6SHuang Shijie /* set UCR1 */
14204444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
14214444dcf1SUwe Kleine-König ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
14224444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
1423b4cdc8f6SHuang Shijie
1424b4cdc8f6SHuang Shijie sport->dma_is_enabled = 1;
1425b4cdc8f6SHuang Shijie }
1426b4cdc8f6SHuang Shijie
imx_uart_disable_dma(struct imx_port * sport)14279d1a50a2SUwe Kleine-König static void imx_uart_disable_dma(struct imx_port *sport)
1428b4cdc8f6SHuang Shijie {
1429676a31d8SSebastian Reichel u32 ucr1;
1430b4cdc8f6SHuang Shijie
1431b4cdc8f6SHuang Shijie /* clear UCR1 */
14324444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
14334444dcf1SUwe Kleine-König ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
14344444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
1435b4cdc8f6SHuang Shijie
14369d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1437184bd70bSLucas Stach
1438b4cdc8f6SHuang Shijie sport->dma_is_enabled = 0;
1439b4cdc8f6SHuang Shijie }
1440b4cdc8f6SHuang Shijie
1441ab4382d2SGreg Kroah-Hartman /* half the RX buffer size */
1442ab4382d2SGreg Kroah-Hartman #define CTSTL 16
1443ab4382d2SGreg Kroah-Hartman
imx_uart_startup(struct uart_port * port)14449d1a50a2SUwe Kleine-König static int imx_uart_startup(struct uart_port *port)
1445ab4382d2SGreg Kroah-Hartman {
1446ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
1447d45fb2e4SSergey Organov int retval;
14484444dcf1SUwe Kleine-König unsigned long flags;
14494238c00bSUwe Kleine-König int dma_is_inited = 0;
1450639949a7SMartin Fuzzey u32 ucr1, ucr2, ucr3, ucr4;
1451ab4382d2SGreg Kroah-Hartman
145228eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_per);
145328eb4274SHuang Shijie if (retval)
1454cb0f0a5fSFabio Estevam return retval;
145528eb4274SHuang Shijie retval = clk_prepare_enable(sport->clk_ipg);
14560c375501SHuang Shijie if (retval) {
14570c375501SHuang Shijie clk_disable_unprepare(sport->clk_per);
1458cb0f0a5fSFabio Estevam return retval;
14590c375501SHuang Shijie }
146028eb4274SHuang Shijie
14619d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1462ab4382d2SGreg Kroah-Hartman
1463ab4382d2SGreg Kroah-Hartman /* disable the DREN bit (Data Ready interrupt enable) before
1464ab4382d2SGreg Kroah-Hartman * requesting IRQs
1465ab4382d2SGreg Kroah-Hartman */
14664444dcf1SUwe Kleine-König ucr4 = imx_uart_readl(sport, UCR4);
1467ab4382d2SGreg Kroah-Hartman
1468ab4382d2SGreg Kroah-Hartman /* set the trigger level for CTS */
14694444dcf1SUwe Kleine-König ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
14704444dcf1SUwe Kleine-König ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1471ab4382d2SGreg Kroah-Hartman
14724444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1473ab4382d2SGreg Kroah-Hartman
14747e11577eSLucas Stach /* Can we enable the DMA support? */
14754238c00bSUwe Kleine-König if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
14764238c00bSUwe Kleine-König dma_is_inited = 1;
14777e11577eSLucas Stach
147853794183SJiada Wang spin_lock_irqsave(&sport->port.lock, flags);
1479d45fb2e4SSergey Organov
1480772f8991SHuang Shijie /* Reset fifo's and state machines */
1481d45fb2e4SSergey Organov imx_uart_soft_reset(sport);
1482ab4382d2SGreg Kroah-Hartman
1483ab4382d2SGreg Kroah-Hartman /*
1484ab4382d2SGreg Kroah-Hartman * Finally, clear and enable interrupts
1485ab4382d2SGreg Kroah-Hartman */
148627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
148727c84426SUwe Kleine-König imx_uart_writel(sport, USR2_ORE, USR2);
1488ab4382d2SGreg Kroah-Hartman
14894444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
14904444dcf1SUwe Kleine-König ucr1 |= UCR1_UARTEN;
14916376cd39SNandor Han if (sport->have_rtscts)
14924444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN;
1493ab4382d2SGreg Kroah-Hartman
14944444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
1495ab4382d2SGreg Kroah-Hartman
14965a08a487SGeorge Hilliard ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
14973ee82c6eSJohan Hovold if (!dma_is_inited)
14984444dcf1SUwe Kleine-König ucr4 |= UCR4_OREN;
14995a08a487SGeorge Hilliard if (sport->inverted_rx)
15005a08a487SGeorge Hilliard ucr4 |= UCR4_INVR;
15014444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr4, UCR4);
15026f026d6bSJiada Wang
15035a08a487SGeorge Hilliard ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
15045a08a487SGeorge Hilliard /*
15055a08a487SGeorge Hilliard * configure tx polarity before enabling tx
15065a08a487SGeorge Hilliard */
15075a08a487SGeorge Hilliard if (sport->inverted_tx)
15085a08a487SGeorge Hilliard ucr3 |= UCR3_INVT;
15095a08a487SGeorge Hilliard
15105a08a487SGeorge Hilliard if (!imx_uart_is_imx1(sport)) {
15115a08a487SGeorge Hilliard ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
15125a08a487SGeorge Hilliard
15135a08a487SGeorge Hilliard if (sport->dte_mode)
15145a08a487SGeorge Hilliard /* disable broken interrupts */
15155a08a487SGeorge Hilliard ucr3 &= ~(UCR3_RI | UCR3_DCD);
15165a08a487SGeorge Hilliard }
15175a08a487SGeorge Hilliard imx_uart_writel(sport, ucr3, UCR3);
15185a08a487SGeorge Hilliard
15194444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
15204444dcf1SUwe Kleine-König ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1521bff09b09SLucas Stach if (!sport->have_rtscts)
15224444dcf1SUwe Kleine-König ucr2 |= UCR2_IRTS;
152316804d68SUwe Kleine-König /*
152416804d68SUwe Kleine-König * make sure the edge sensitive RTS-irq is disabled,
152516804d68SUwe Kleine-König * we're using RTSD instead.
152616804d68SUwe Kleine-König */
15279d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport))
15284444dcf1SUwe Kleine-König ucr2 &= ~UCR2_RTSEN;
15294444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
1530ab4382d2SGreg Kroah-Hartman
1531ab4382d2SGreg Kroah-Hartman /*
1532ab4382d2SGreg Kroah-Hartman * Enable modem status interrupts
1533ab4382d2SGreg Kroah-Hartman */
15349d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port);
153518a42088SPeter Senna Tschudin
153676821e22SUwe Kleine-König if (dma_is_inited) {
15379d1a50a2SUwe Kleine-König imx_uart_enable_dma(sport);
15389d1a50a2SUwe Kleine-König imx_uart_start_rx_dma(sport);
153976821e22SUwe Kleine-König } else {
154076821e22SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
154176821e22SUwe Kleine-König ucr1 |= UCR1_RRDYEN;
154276821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
154381ca8e82SUwe Kleine-König
154481ca8e82SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
154581ca8e82SUwe Kleine-König ucr2 |= UCR2_ATEN;
154681ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
154776821e22SUwe Kleine-König }
154818a42088SPeter Senna Tschudin
1549639949a7SMartin Fuzzey imx_uart_disable_loopback_rs485(sport);
155079d0224fSMarek Vasut
1551ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags);
1552ab4382d2SGreg Kroah-Hartman
1553ab4382d2SGreg Kroah-Hartman return 0;
1554ab4382d2SGreg Kroah-Hartman }
1555ab4382d2SGreg Kroah-Hartman
imx_uart_shutdown(struct uart_port * port)15569d1a50a2SUwe Kleine-König static void imx_uart_shutdown(struct uart_port *port)
1557ab4382d2SGreg Kroah-Hartman {
1558ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
15599ec1882dSXinyu Chen unsigned long flags;
156079d0224fSMarek Vasut u32 ucr1, ucr2, ucr4, uts;
1561ab4382d2SGreg Kroah-Hartman
1562b4cdc8f6SHuang Shijie if (sport->dma_is_enabled) {
1563e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_tx);
15647722c240SSebastian Reichel if (sport->dma_is_txing) {
15657722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
15667722c240SSebastian Reichel sport->dma_tx_nents, DMA_TO_DEVICE);
15677722c240SSebastian Reichel sport->dma_is_txing = 0;
15687722c240SSebastian Reichel }
1569e5e89602SFabien Lahoudere dmaengine_terminate_sync(sport->dma_chan_rx);
15707722c240SSebastian Reichel if (sport->dma_is_rxing) {
15717722c240SSebastian Reichel dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
15727722c240SSebastian Reichel 1, DMA_FROM_DEVICE);
15737722c240SSebastian Reichel sport->dma_is_rxing = 0;
15747722c240SSebastian Reichel }
15759d297239SNandor Han
157673631813SJiada Wang spin_lock_irqsave(&sport->port.lock, flags);
15779d1a50a2SUwe Kleine-König imx_uart_stop_tx(port);
15789d1a50a2SUwe Kleine-König imx_uart_stop_rx(port);
15799d1a50a2SUwe Kleine-König imx_uart_disable_dma(sport);
158073631813SJiada Wang spin_unlock_irqrestore(&sport->port.lock, flags);
1581b4cdc8f6SHuang Shijie imx_uart_dma_exit(sport);
1582b4cdc8f6SHuang Shijie }
1583b4cdc8f6SHuang Shijie
158458362d5bSUwe Kleine-König mctrl_gpio_disable_ms(sport->gpios);
158558362d5bSUwe Kleine-König
15869ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags);
15874444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
15880fdf1787SSebastian Reichel ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
15894444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
15909ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags);
1591ab4382d2SGreg Kroah-Hartman
1592ab4382d2SGreg Kroah-Hartman /*
1593ab4382d2SGreg Kroah-Hartman * Stop our timer.
1594ab4382d2SGreg Kroah-Hartman */
1595ab4382d2SGreg Kroah-Hartman del_timer_sync(&sport->timer);
1596ab4382d2SGreg Kroah-Hartman
1597ab4382d2SGreg Kroah-Hartman /*
1598ab4382d2SGreg Kroah-Hartman * Disable all interrupts, port and break condition.
1599ab4382d2SGreg Kroah-Hartman */
1600ab4382d2SGreg Kroah-Hartman
16019ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags);
1602edd64f30SMatthias Schiffer
16034444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
1604509597ebSSherry Sun ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1605509597ebSSherry Sun UCR1_ATDMAEN | UCR1_SNDBRK);
160679d0224fSMarek Vasut /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
160779d0224fSMarek Vasut if (port->rs485.flags & SER_RS485_ENABLED &&
160879d0224fSMarek Vasut port->rs485.flags & SER_RS485_RTS_ON_SEND &&
160979d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) {
161079d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
161179d0224fSMarek Vasut uts |= UTS_LOOP;
161279d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
161379d0224fSMarek Vasut ucr1 |= UCR1_UARTEN;
161479d0224fSMarek Vasut } else {
161579d0224fSMarek Vasut ucr1 &= ~UCR1_UARTEN;
161679d0224fSMarek Vasut }
16174444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
1618edd64f30SMatthias Schiffer
1619edd64f30SMatthias Schiffer ucr4 = imx_uart_readl(sport, UCR4);
1620028e0838SFugang Duan ucr4 &= ~UCR4_TCEN;
1621edd64f30SMatthias Schiffer imx_uart_writel(sport, ucr4, UCR4);
1622edd64f30SMatthias Schiffer
16239ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags);
162428eb4274SHuang Shijie
162528eb4274SHuang Shijie clk_disable_unprepare(sport->clk_per);
162628eb4274SHuang Shijie clk_disable_unprepare(sport->clk_ipg);
1627ab4382d2SGreg Kroah-Hartman }
1628ab4382d2SGreg Kroah-Hartman
16296aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)16309d1a50a2SUwe Kleine-König static void imx_uart_flush_buffer(struct uart_port *port)
1631eb56b7edSHuang Shijie {
1632eb56b7edSHuang Shijie struct imx_port *sport = (struct imx_port *)port;
163382e86ae9SDirk Behme struct scatterlist *sgl = &sport->tx_sgl[0];
1634eb56b7edSHuang Shijie
163582e86ae9SDirk Behme if (!sport->dma_chan_tx)
163682e86ae9SDirk Behme return;
163782e86ae9SDirk Behme
1638eb56b7edSHuang Shijie sport->tx_bytes = 0;
1639eb56b7edSHuang Shijie dmaengine_terminate_all(sport->dma_chan_tx);
164082e86ae9SDirk Behme if (sport->dma_is_txing) {
16414444dcf1SUwe Kleine-König u32 ucr1;
16424444dcf1SUwe Kleine-König
164382e86ae9SDirk Behme dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
164482e86ae9SDirk Behme DMA_TO_DEVICE);
16454444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
16464444dcf1SUwe Kleine-König ucr1 &= ~UCR1_TXDMAEN;
16474444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
16480f7bdbd2SMartyn Welch sport->dma_is_txing = 0;
1649eb56b7edSHuang Shijie }
1650934084a9SFabio Estevam
1651d45fb2e4SSergey Organov imx_uart_soft_reset(sport);
1652934084a9SFabio Estevam
1653eb56b7edSHuang Shijie }
1654eb56b7edSHuang Shijie
1655ab4382d2SGreg Kroah-Hartman static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)16569d1a50a2SUwe Kleine-König imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1657bec5b814SIlpo Järvinen const struct ktermios *old)
1658ab4382d2SGreg Kroah-Hartman {
1659ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
1660ab4382d2SGreg Kroah-Hartman unsigned long flags;
166185f30fbfSSergey Organov u32 ucr2, old_ucr2, ufcr;
166258362d5bSUwe Kleine-König unsigned int baud, quot;
1663ab4382d2SGreg Kroah-Hartman unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
16644444dcf1SUwe Kleine-König unsigned long div;
1665d47bcb4aSSergey Organov unsigned long num, denom, old_ubir, old_ubmr;
1666ab4382d2SGreg Kroah-Hartman uint64_t tdiv64;
1667ab4382d2SGreg Kroah-Hartman
1668ab4382d2SGreg Kroah-Hartman /*
1669ab4382d2SGreg Kroah-Hartman * We only support CS7 and CS8.
1670ab4382d2SGreg Kroah-Hartman */
1671ab4382d2SGreg Kroah-Hartman while ((termios->c_cflag & CSIZE) != CS7 &&
1672ab4382d2SGreg Kroah-Hartman (termios->c_cflag & CSIZE) != CS8) {
1673ab4382d2SGreg Kroah-Hartman termios->c_cflag &= ~CSIZE;
1674ab4382d2SGreg Kroah-Hartman termios->c_cflag |= old_csize;
1675ab4382d2SGreg Kroah-Hartman old_csize = CS8;
1676ab4382d2SGreg Kroah-Hartman }
1677ab4382d2SGreg Kroah-Hartman
16784e828c3eSSergey Organov del_timer_sync(&sport->timer);
16794e828c3eSSergey Organov
16804e828c3eSSergey Organov /*
16814e828c3eSSergey Organov * Ask the core to calculate the divisor for us.
16824e828c3eSSergey Organov */
16834e828c3eSSergey Organov baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
16844e828c3eSSergey Organov quot = uart_get_divisor(port, baud);
16854e828c3eSSergey Organov
16864e828c3eSSergey Organov spin_lock_irqsave(&sport->port.lock, flags);
16874e828c3eSSergey Organov
1688011bd05dSSergey Organov /*
1689011bd05dSSergey Organov * Read current UCR2 and save it for future use, then clear all the bits
1690011bd05dSSergey Organov * except those we will or may need to preserve.
1691011bd05dSSergey Organov */
1692011bd05dSSergey Organov old_ucr2 = imx_uart_readl(sport, UCR2);
1693011bd05dSSergey Organov ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1694011bd05dSSergey Organov
1695011bd05dSSergey Organov ucr2 |= UCR2_SRST | UCR2_IRTS;
169641ffa48eSSergey Organov if ((termios->c_cflag & CSIZE) == CS8)
169741ffa48eSSergey Organov ucr2 |= UCR2_WS;
1698ab4382d2SGreg Kroah-Hartman
1699ddf89e75SSergey Organov if (!sport->have_rtscts)
1700ddf89e75SSergey Organov termios->c_cflag &= ~CRTSCTS;
170117b8f2a3SUwe Kleine-König
170212fe59f9SFabio Estevam if (port->rs485.flags & SER_RS485_ENABLED) {
170317b8f2a3SUwe Kleine-König /*
170417b8f2a3SUwe Kleine-König * RTS is mandatory for rs485 operation, so keep
170517b8f2a3SUwe Kleine-König * it under manual control and keep transmitter
170617b8f2a3SUwe Kleine-König * disabled.
170717b8f2a3SUwe Kleine-König */
170858362d5bSUwe Kleine-König if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
17099d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2);
17101a613626SFabio Estevam else
17119d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2);
171258362d5bSUwe Kleine-König
1713b777b5deSSergey Organov } else if (termios->c_cflag & CRTSCTS) {
1714b777b5deSSergey Organov /*
1715b777b5deSSergey Organov * Only let receiver control RTS output if we were not requested
1716b777b5deSSergey Organov * to have RTS inactive (which then should take precedence).
1717b777b5deSSergey Organov */
1718b777b5deSSergey Organov if (ucr2 & UCR2_CTS)
1719b777b5deSSergey Organov ucr2 |= UCR2_CTSC;
1720b777b5deSSergey Organov }
1721ddf89e75SSergey Organov
1722ddf89e75SSergey Organov if (termios->c_cflag & CRTSCTS)
1723ddf89e75SSergey Organov ucr2 &= ~UCR2_IRTS;
1724ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & CSTOPB)
1725ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_STPB;
1726ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARENB) {
1727ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PREN;
1728ab4382d2SGreg Kroah-Hartman if (termios->c_cflag & PARODD)
1729ab4382d2SGreg Kroah-Hartman ucr2 |= UCR2_PROE;
1730ab4382d2SGreg Kroah-Hartman }
1731ab4382d2SGreg Kroah-Hartman
1732ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask = 0;
1733ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & INPCK)
1734ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1735ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & (BRKINT | PARMRK))
1736ab4382d2SGreg Kroah-Hartman sport->port.read_status_mask |= URXD_BRK;
1737ab4382d2SGreg Kroah-Hartman
1738ab4382d2SGreg Kroah-Hartman /*
1739ab4382d2SGreg Kroah-Hartman * Characters to ignore
1740ab4382d2SGreg Kroah-Hartman */
1741ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask = 0;
1742ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR)
1743865cea85SEric Nelson sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1744ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNBRK) {
1745ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_BRK;
1746ab4382d2SGreg Kroah-Hartman /*
1747ab4382d2SGreg Kroah-Hartman * If we're ignoring parity and break indicators,
1748ab4382d2SGreg Kroah-Hartman * ignore overruns too (for real raw support).
1749ab4382d2SGreg Kroah-Hartman */
1750ab4382d2SGreg Kroah-Hartman if (termios->c_iflag & IGNPAR)
1751ab4382d2SGreg Kroah-Hartman sport->port.ignore_status_mask |= URXD_OVRRUN;
1752ab4382d2SGreg Kroah-Hartman }
1753ab4382d2SGreg Kroah-Hartman
175455d8693aSJiada Wang if ((termios->c_cflag & CREAD) == 0)
175555d8693aSJiada Wang sport->port.ignore_status_mask |= URXD_DUMMY_READ;
175655d8693aSJiada Wang
1757ab4382d2SGreg Kroah-Hartman /*
1758ab4382d2SGreg Kroah-Hartman * Update the per-port timeout.
1759ab4382d2SGreg Kroah-Hartman */
1760ab4382d2SGreg Kroah-Hartman uart_update_timeout(port, termios->c_cflag, baud);
1761ab4382d2SGreg Kroah-Hartman
176209bd00f6SHubert Feurstein /* custom-baudrate handling */
176309bd00f6SHubert Feurstein div = sport->port.uartclk / (baud * 16);
176409bd00f6SHubert Feurstein if (baud == 38400 && quot != div)
176509bd00f6SHubert Feurstein baud = sport->port.uartclk / (quot * 16);
176609bd00f6SHubert Feurstein
1767ab4382d2SGreg Kroah-Hartman div = sport->port.uartclk / (baud * 16);
1768ab4382d2SGreg Kroah-Hartman if (div > 7)
1769ab4382d2SGreg Kroah-Hartman div = 7;
1770ab4382d2SGreg Kroah-Hartman if (!div)
1771ab4382d2SGreg Kroah-Hartman div = 1;
1772ab4382d2SGreg Kroah-Hartman
1773ab4382d2SGreg Kroah-Hartman rational_best_approximation(16 * div * baud, sport->port.uartclk,
1774ab4382d2SGreg Kroah-Hartman 1 << 16, 1 << 16, &num, &denom);
1775ab4382d2SGreg Kroah-Hartman
1776ab4382d2SGreg Kroah-Hartman tdiv64 = sport->port.uartclk;
1777ab4382d2SGreg Kroah-Hartman tdiv64 *= num;
1778ab4382d2SGreg Kroah-Hartman do_div(tdiv64, denom * 16 * div);
1779ab4382d2SGreg Kroah-Hartman tty_termios_encode_baud_rate(termios,
1780ab4382d2SGreg Kroah-Hartman (speed_t)tdiv64, (speed_t)tdiv64);
1781ab4382d2SGreg Kroah-Hartman
1782ab4382d2SGreg Kroah-Hartman num -= 1;
1783ab4382d2SGreg Kroah-Hartman denom -= 1;
1784ab4382d2SGreg Kroah-Hartman
178527c84426SUwe Kleine-König ufcr = imx_uart_readl(sport, UFCR);
1786ab4382d2SGreg Kroah-Hartman ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
178727c84426SUwe Kleine-König imx_uart_writel(sport, ufcr, UFCR);
1788ab4382d2SGreg Kroah-Hartman
1789d47bcb4aSSergey Organov /*
1790d47bcb4aSSergey Organov * Two registers below should always be written both and in this
1791d47bcb4aSSergey Organov * particular order. One consequence is that we need to check if any of
1792d47bcb4aSSergey Organov * them changes and then update both. We do need the check for change
1793d47bcb4aSSergey Organov * as even writing the same values seem to "restart"
1794d47bcb4aSSergey Organov * transmission/receiving logic in the hardware, that leads to data
1795d47bcb4aSSergey Organov * breakage even when rate doesn't in fact change. E.g., user switches
1796d47bcb4aSSergey Organov * RTS/CTS handshake and suddenly gets broken bytes.
1797d47bcb4aSSergey Organov */
1798d47bcb4aSSergey Organov old_ubir = imx_uart_readl(sport, UBIR);
1799d47bcb4aSSergey Organov old_ubmr = imx_uart_readl(sport, UBMR);
1800d47bcb4aSSergey Organov if (old_ubir != num || old_ubmr != denom) {
180127c84426SUwe Kleine-König imx_uart_writel(sport, num, UBIR);
180227c84426SUwe Kleine-König imx_uart_writel(sport, denom, UBMR);
1803d47bcb4aSSergey Organov }
1804ab4382d2SGreg Kroah-Hartman
18059d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport))
180627c84426SUwe Kleine-König imx_uart_writel(sport, sport->port.uartclk / div / 1000,
180727c84426SUwe Kleine-König IMX21_ONEMS);
1808ab4382d2SGreg Kroah-Hartman
1809011bd05dSSergey Organov imx_uart_writel(sport, ucr2, UCR2);
1810ab4382d2SGreg Kroah-Hartman
1811ab4382d2SGreg Kroah-Hartman if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
18129d1a50a2SUwe Kleine-König imx_uart_enable_ms(&sport->port);
1813ab4382d2SGreg Kroah-Hartman
1814ab4382d2SGreg Kroah-Hartman spin_unlock_irqrestore(&sport->port.lock, flags);
1815ab4382d2SGreg Kroah-Hartman }
1816ab4382d2SGreg Kroah-Hartman
imx_uart_type(struct uart_port * port)18179d1a50a2SUwe Kleine-König static const char *imx_uart_type(struct uart_port *port)
1818ab4382d2SGreg Kroah-Hartman {
181946ce64bbSUwe Kleine-König return port->type == PORT_IMX ? "IMX" : NULL;
1820ab4382d2SGreg Kroah-Hartman }
1821ab4382d2SGreg Kroah-Hartman
1822ab4382d2SGreg Kroah-Hartman /*
1823ab4382d2SGreg Kroah-Hartman * Configure/autoconfigure the port.
1824ab4382d2SGreg Kroah-Hartman */
imx_uart_config_port(struct uart_port * port,int flags)18259d1a50a2SUwe Kleine-König static void imx_uart_config_port(struct uart_port *port, int flags)
1826ab4382d2SGreg Kroah-Hartman {
1827da82f997SAlexander Shiyan if (flags & UART_CONFIG_TYPE)
182846ce64bbSUwe Kleine-König port->type = PORT_IMX;
1829ab4382d2SGreg Kroah-Hartman }
1830ab4382d2SGreg Kroah-Hartman
1831ab4382d2SGreg Kroah-Hartman /*
1832ab4382d2SGreg Kroah-Hartman * Verify the new serial_struct (for TIOCSSERIAL).
1833ab4382d2SGreg Kroah-Hartman * The only change we allow are to the flags and type, and
1834ab4382d2SGreg Kroah-Hartman * even then only between PORT_IMX and PORT_UNKNOWN
1835ab4382d2SGreg Kroah-Hartman */
1836ab4382d2SGreg Kroah-Hartman static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)18379d1a50a2SUwe Kleine-König imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1838ab4382d2SGreg Kroah-Hartman {
1839ab4382d2SGreg Kroah-Hartman int ret = 0;
1840ab4382d2SGreg Kroah-Hartman
1841ab4382d2SGreg Kroah-Hartman if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1842ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
184346ce64bbSUwe Kleine-König if (port->irq != ser->irq)
1844ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
1845ab4382d2SGreg Kroah-Hartman if (ser->io_type != UPIO_MEM)
1846ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
184746ce64bbSUwe Kleine-König if (port->uartclk / 16 != ser->baud_base)
1848ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
184946ce64bbSUwe Kleine-König if (port->mapbase != (unsigned long)ser->iomem_base)
1850ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
185146ce64bbSUwe Kleine-König if (port->iobase != ser->port)
1852ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
1853ab4382d2SGreg Kroah-Hartman if (ser->hub6 != 0)
1854ab4382d2SGreg Kroah-Hartman ret = -EINVAL;
1855ab4382d2SGreg Kroah-Hartman return ret;
1856ab4382d2SGreg Kroah-Hartman }
1857ab4382d2SGreg Kroah-Hartman
185801f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL)
18596b8bdad9SDaniel Thompson
imx_uart_poll_init(struct uart_port * port)18609d1a50a2SUwe Kleine-König static int imx_uart_poll_init(struct uart_port *port)
18616b8bdad9SDaniel Thompson {
18626b8bdad9SDaniel Thompson struct imx_port *sport = (struct imx_port *)port;
18636b8bdad9SDaniel Thompson unsigned long flags;
18644444dcf1SUwe Kleine-König u32 ucr1, ucr2;
18656b8bdad9SDaniel Thompson int retval;
18666b8bdad9SDaniel Thompson
18676b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_ipg);
18686b8bdad9SDaniel Thompson if (retval)
18696b8bdad9SDaniel Thompson return retval;
18706b8bdad9SDaniel Thompson retval = clk_prepare_enable(sport->clk_per);
18716b8bdad9SDaniel Thompson if (retval)
18726b8bdad9SDaniel Thompson clk_disable_unprepare(sport->clk_ipg);
18736b8bdad9SDaniel Thompson
18749d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
18756b8bdad9SDaniel Thompson
18766b8bdad9SDaniel Thompson spin_lock_irqsave(&sport->port.lock, flags);
18776b8bdad9SDaniel Thompson
187876821e22SUwe Kleine-König /*
187976821e22SUwe Kleine-König * Be careful about the order of enabling bits here. First enable the
188076821e22SUwe Kleine-König * receiver (UARTEN + RXEN) and only then the corresponding irqs.
188176821e22SUwe Kleine-König * This prevents that a character that already sits in the RX fifo is
188276821e22SUwe Kleine-König * triggering an irq but the try to fetch it from there results in an
188376821e22SUwe Kleine-König * exception because UARTEN or RXEN is still off.
188476821e22SUwe Kleine-König */
18854444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
188676821e22SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
188776821e22SUwe Kleine-König
18889d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport))
18894444dcf1SUwe Kleine-König ucr1 |= IMX1_UCR1_UARTCLKEN;
18906b8bdad9SDaniel Thompson
189176821e22SUwe Kleine-König ucr1 |= UCR1_UARTEN;
1892c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
189376821e22SUwe Kleine-König
1894aef1b6a2SMingrui Ren ucr2 |= UCR2_RXEN | UCR2_TXEN;
189581ca8e82SUwe Kleine-König ucr2 &= ~UCR2_ATEN;
189676821e22SUwe Kleine-König
189776821e22SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
18984444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
18996b8bdad9SDaniel Thompson
190076821e22SUwe Kleine-König /* now enable irqs */
190176821e22SUwe Kleine-König imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
190281ca8e82SUwe Kleine-König imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
190376821e22SUwe Kleine-König
19046b8bdad9SDaniel Thompson spin_unlock_irqrestore(&sport->port.lock, flags);
19056b8bdad9SDaniel Thompson
19066b8bdad9SDaniel Thompson return 0;
19076b8bdad9SDaniel Thompson }
19086b8bdad9SDaniel Thompson
imx_uart_poll_get_char(struct uart_port * port)19099d1a50a2SUwe Kleine-König static int imx_uart_poll_get_char(struct uart_port *port)
191001f56abdSSaleem Abdulrasool {
191127c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port;
191227c84426SUwe Kleine-König if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
191326c47412SDirk Behme return NO_POLL_CHAR;
191401f56abdSSaleem Abdulrasool
191527c84426SUwe Kleine-König return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
191601f56abdSSaleem Abdulrasool }
191701f56abdSSaleem Abdulrasool
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)19189d1a50a2SUwe Kleine-König static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
191901f56abdSSaleem Abdulrasool {
192027c84426SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port;
192101f56abdSSaleem Abdulrasool unsigned int status;
192201f56abdSSaleem Abdulrasool
192301f56abdSSaleem Abdulrasool /* drain */
192401f56abdSSaleem Abdulrasool do {
192527c84426SUwe Kleine-König status = imx_uart_readl(sport, USR1);
192601f56abdSSaleem Abdulrasool } while (~status & USR1_TRDY);
192701f56abdSSaleem Abdulrasool
192801f56abdSSaleem Abdulrasool /* write */
192927c84426SUwe Kleine-König imx_uart_writel(sport, c, URTX0);
193001f56abdSSaleem Abdulrasool
193101f56abdSSaleem Abdulrasool /* flush */
193201f56abdSSaleem Abdulrasool do {
193327c84426SUwe Kleine-König status = imx_uart_readl(sport, USR2);
193401f56abdSSaleem Abdulrasool } while (~status & USR2_TXDC);
193501f56abdSSaleem Abdulrasool }
193601f56abdSSaleem Abdulrasool #endif
193701f56abdSSaleem Abdulrasool
19386aed2a88SUwe Kleine-König /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1939ae50bb27SIlpo Järvinen static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
194017b8f2a3SUwe Kleine-König struct serial_rs485 *rs485conf)
194117b8f2a3SUwe Kleine-König {
194217b8f2a3SUwe Kleine-König struct imx_port *sport = (struct imx_port *)port;
19434444dcf1SUwe Kleine-König u32 ucr2;
194417b8f2a3SUwe Kleine-König
194517b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_ENABLED) {
19466d215f83SStefan Agner /* Enable receiver if low-active RTS signal is requested */
19476d215f83SStefan Agner if (sport->have_rtscts && !sport->have_rtsgpio &&
19486d215f83SStefan Agner !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
19496d215f83SStefan Agner rs485conf->flags |= SER_RS485_RX_DURING_TX;
19506d215f83SStefan Agner
195117b8f2a3SUwe Kleine-König /* disable transmitter */
19524444dcf1SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
195317b8f2a3SUwe Kleine-König if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
19549d1a50a2SUwe Kleine-König imx_uart_rts_active(sport, &ucr2);
19551a613626SFabio Estevam else
19569d1a50a2SUwe Kleine-König imx_uart_rts_inactive(sport, &ucr2);
19574444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr2, UCR2);
195817b8f2a3SUwe Kleine-König }
195917b8f2a3SUwe Kleine-König
19607d1cadcaSBaruch Siach /* Make sure Rx is enabled in case Tx is active with Rx disabled */
19617d1cadcaSBaruch Siach if (!(rs485conf->flags & SER_RS485_ENABLED) ||
196276821e22SUwe Kleine-König rs485conf->flags & SER_RS485_RX_DURING_TX)
19639d1a50a2SUwe Kleine-König imx_uart_start_rx(port);
19647d1cadcaSBaruch Siach
196517b8f2a3SUwe Kleine-König return 0;
196617b8f2a3SUwe Kleine-König }
196717b8f2a3SUwe Kleine-König
19689d1a50a2SUwe Kleine-König static const struct uart_ops imx_uart_pops = {
19699d1a50a2SUwe Kleine-König .tx_empty = imx_uart_tx_empty,
19709d1a50a2SUwe Kleine-König .set_mctrl = imx_uart_set_mctrl,
19719d1a50a2SUwe Kleine-König .get_mctrl = imx_uart_get_mctrl,
19729d1a50a2SUwe Kleine-König .stop_tx = imx_uart_stop_tx,
19739d1a50a2SUwe Kleine-König .start_tx = imx_uart_start_tx,
19749d1a50a2SUwe Kleine-König .stop_rx = imx_uart_stop_rx,
19759d1a50a2SUwe Kleine-König .enable_ms = imx_uart_enable_ms,
19769d1a50a2SUwe Kleine-König .break_ctl = imx_uart_break_ctl,
19779d1a50a2SUwe Kleine-König .startup = imx_uart_startup,
19789d1a50a2SUwe Kleine-König .shutdown = imx_uart_shutdown,
19799d1a50a2SUwe Kleine-König .flush_buffer = imx_uart_flush_buffer,
19809d1a50a2SUwe Kleine-König .set_termios = imx_uart_set_termios,
19819d1a50a2SUwe Kleine-König .type = imx_uart_type,
19829d1a50a2SUwe Kleine-König .config_port = imx_uart_config_port,
19839d1a50a2SUwe Kleine-König .verify_port = imx_uart_verify_port,
198401f56abdSSaleem Abdulrasool #if defined(CONFIG_CONSOLE_POLL)
19859d1a50a2SUwe Kleine-König .poll_init = imx_uart_poll_init,
19869d1a50a2SUwe Kleine-König .poll_get_char = imx_uart_poll_get_char,
19879d1a50a2SUwe Kleine-König .poll_put_char = imx_uart_poll_put_char,
198801f56abdSSaleem Abdulrasool #endif
1989ab4382d2SGreg Kroah-Hartman };
1990ab4382d2SGreg Kroah-Hartman
19919d1a50a2SUwe Kleine-König static struct imx_port *imx_uart_ports[UART_NR];
1992ab4382d2SGreg Kroah-Hartman
19930db4f9b9SFugang Duan #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)19943f8bab17SJiri Slaby static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1995ab4382d2SGreg Kroah-Hartman {
1996ab4382d2SGreg Kroah-Hartman struct imx_port *sport = (struct imx_port *)port;
1997ab4382d2SGreg Kroah-Hartman
19989d1a50a2SUwe Kleine-König while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1999ab4382d2SGreg Kroah-Hartman barrier();
2000ab4382d2SGreg Kroah-Hartman
200127c84426SUwe Kleine-König imx_uart_writel(sport, ch, URTX0);
2002ab4382d2SGreg Kroah-Hartman }
2003ab4382d2SGreg Kroah-Hartman
2004ab4382d2SGreg Kroah-Hartman /*
2005ab4382d2SGreg Kroah-Hartman * Interrupts are disabled on entering
2006ab4382d2SGreg Kroah-Hartman */
2007ab4382d2SGreg Kroah-Hartman static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)20089d1a50a2SUwe Kleine-König imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2009ab4382d2SGreg Kroah-Hartman {
20109d1a50a2SUwe Kleine-König struct imx_port *sport = imx_uart_ports[co->index];
20110ad5a814SDirk Behme struct imx_port_ucrs old_ucr;
201218ee37e1SJohan Hovold unsigned long flags;
2013*982ae337SEsben Haabendal unsigned int ucr1, usr2;
2014677fe555SThomas Gleixner int locked = 1;
20159ec1882dSXinyu Chen
2016677fe555SThomas Gleixner if (sport->port.sysrq)
2017677fe555SThomas Gleixner locked = 0;
2018677fe555SThomas Gleixner else if (oops_in_progress)
2019677fe555SThomas Gleixner locked = spin_trylock_irqsave(&sport->port.lock, flags);
2020677fe555SThomas Gleixner else
20219ec1882dSXinyu Chen spin_lock_irqsave(&sport->port.lock, flags);
2022ab4382d2SGreg Kroah-Hartman
2023ab4382d2SGreg Kroah-Hartman /*
20240ad5a814SDirk Behme * First, save UCR1/2/3 and then disable interrupts
2025ab4382d2SGreg Kroah-Hartman */
20269d1a50a2SUwe Kleine-König imx_uart_ucrs_save(sport, &old_ucr);
20270ad5a814SDirk Behme ucr1 = old_ucr.ucr1;
2028ab4382d2SGreg Kroah-Hartman
20299d1a50a2SUwe Kleine-König if (imx_uart_is_imx1(sport))
2030fe6b540aSShawn Guo ucr1 |= IMX1_UCR1_UARTCLKEN;
2031ab4382d2SGreg Kroah-Hartman ucr1 |= UCR1_UARTEN;
2032c514a6f8SSergey Organov ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2033ab4382d2SGreg Kroah-Hartman
203427c84426SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
2035ab4382d2SGreg Kroah-Hartman
203627c84426SUwe Kleine-König imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2037ab4382d2SGreg Kroah-Hartman
20389d1a50a2SUwe Kleine-König uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2039ab4382d2SGreg Kroah-Hartman
2040ab4382d2SGreg Kroah-Hartman /*
2041ab4382d2SGreg Kroah-Hartman * Finally, wait for transmitter to become empty
20420ad5a814SDirk Behme * and restore UCR1/2/3
2043ab4382d2SGreg Kroah-Hartman */
2044*982ae337SEsben Haabendal read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2045*982ae337SEsben Haabendal 0, USEC_PER_SEC, false, sport, USR2);
20469d1a50a2SUwe Kleine-König imx_uart_ucrs_restore(sport, &old_ucr);
20479ec1882dSXinyu Chen
2048677fe555SThomas Gleixner if (locked)
20499ec1882dSXinyu Chen spin_unlock_irqrestore(&sport->port.lock, flags);
2050ab4382d2SGreg Kroah-Hartman }
2051ab4382d2SGreg Kroah-Hartman
2052ab4382d2SGreg Kroah-Hartman /*
2053ab4382d2SGreg Kroah-Hartman * If the port was already initialised (eg, by a boot loader),
2054ab4382d2SGreg Kroah-Hartman * try to determine the current setup.
2055ab4382d2SGreg Kroah-Hartman */
20566d0d1b5aSStefan Agner static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)20579d1a50a2SUwe Kleine-König imx_uart_console_get_options(struct imx_port *sport, int *baud,
2058ab4382d2SGreg Kroah-Hartman int *parity, int *bits)
2059ab4382d2SGreg Kroah-Hartman {
2060ab4382d2SGreg Kroah-Hartman
206127c84426SUwe Kleine-König if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2062ab4382d2SGreg Kroah-Hartman /* ok, the port was enabled */
2063ab4382d2SGreg Kroah-Hartman unsigned int ucr2, ubir, ubmr, uartclk;
2064ab4382d2SGreg Kroah-Hartman unsigned int baud_raw;
2065ab4382d2SGreg Kroah-Hartman unsigned int ucfr_rfdiv;
2066ab4382d2SGreg Kroah-Hartman
206727c84426SUwe Kleine-König ucr2 = imx_uart_readl(sport, UCR2);
2068ab4382d2SGreg Kroah-Hartman
2069ab4382d2SGreg Kroah-Hartman *parity = 'n';
2070ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PREN) {
2071ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_PROE)
2072ab4382d2SGreg Kroah-Hartman *parity = 'o';
2073ab4382d2SGreg Kroah-Hartman else
2074ab4382d2SGreg Kroah-Hartman *parity = 'e';
2075ab4382d2SGreg Kroah-Hartman }
2076ab4382d2SGreg Kroah-Hartman
2077ab4382d2SGreg Kroah-Hartman if (ucr2 & UCR2_WS)
2078ab4382d2SGreg Kroah-Hartman *bits = 8;
2079ab4382d2SGreg Kroah-Hartman else
2080ab4382d2SGreg Kroah-Hartman *bits = 7;
2081ab4382d2SGreg Kroah-Hartman
208227c84426SUwe Kleine-König ubir = imx_uart_readl(sport, UBIR) & 0xffff;
208327c84426SUwe Kleine-König ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2084ab4382d2SGreg Kroah-Hartman
208527c84426SUwe Kleine-König ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2086ab4382d2SGreg Kroah-Hartman if (ucfr_rfdiv == 6)
2087ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 7;
2088ab4382d2SGreg Kroah-Hartman else
2089ab4382d2SGreg Kroah-Hartman ucfr_rfdiv = 6 - ucfr_rfdiv;
2090ab4382d2SGreg Kroah-Hartman
20913a9465faSSascha Hauer uartclk = clk_get_rate(sport->clk_per);
2092ab4382d2SGreg Kroah-Hartman uartclk /= ucfr_rfdiv;
2093ab4382d2SGreg Kroah-Hartman
2094ab4382d2SGreg Kroah-Hartman { /*
2095ab4382d2SGreg Kroah-Hartman * The next code provides exact computation of
2096ab4382d2SGreg Kroah-Hartman * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2097ab4382d2SGreg Kroah-Hartman * without need of float support or long long division,
2098ab4382d2SGreg Kroah-Hartman * which would be required to prevent 32bit arithmetic overflow
2099ab4382d2SGreg Kroah-Hartman */
2100ab4382d2SGreg Kroah-Hartman unsigned int mul = ubir + 1;
2101ab4382d2SGreg Kroah-Hartman unsigned int div = 16 * (ubmr + 1);
2102ab4382d2SGreg Kroah-Hartman unsigned int rem = uartclk % div;
2103ab4382d2SGreg Kroah-Hartman
2104ab4382d2SGreg Kroah-Hartman baud_raw = (uartclk / div) * mul;
2105ab4382d2SGreg Kroah-Hartman baud_raw += (rem * mul + div / 2) / div;
2106ab4382d2SGreg Kroah-Hartman *baud = (baud_raw + 50) / 100 * 100;
2107ab4382d2SGreg Kroah-Hartman }
2108ab4382d2SGreg Kroah-Hartman
2109ab4382d2SGreg Kroah-Hartman if (*baud != baud_raw)
2110f5a9e5f7SFabio Estevam dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2111ab4382d2SGreg Kroah-Hartman baud_raw, *baud);
2112ab4382d2SGreg Kroah-Hartman }
2113ab4382d2SGreg Kroah-Hartman }
2114ab4382d2SGreg Kroah-Hartman
21156d0d1b5aSStefan Agner static int
imx_uart_console_setup(struct console * co,char * options)21169d1a50a2SUwe Kleine-König imx_uart_console_setup(struct console *co, char *options)
2117ab4382d2SGreg Kroah-Hartman {
2118ab4382d2SGreg Kroah-Hartman struct imx_port *sport;
2119ab4382d2SGreg Kroah-Hartman int baud = 9600;
2120ab4382d2SGreg Kroah-Hartman int bits = 8;
2121ab4382d2SGreg Kroah-Hartman int parity = 'n';
2122ab4382d2SGreg Kroah-Hartman int flow = 'n';
21231cf93e0dSHuang Shijie int retval;
2124ab4382d2SGreg Kroah-Hartman
2125ab4382d2SGreg Kroah-Hartman /*
2126ab4382d2SGreg Kroah-Hartman * Check whether an invalid uart number has been specified, and
2127ab4382d2SGreg Kroah-Hartman * if so, search for the first available port that does have
2128ab4382d2SGreg Kroah-Hartman * console support.
2129ab4382d2SGreg Kroah-Hartman */
21309d1a50a2SUwe Kleine-König if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2131ab4382d2SGreg Kroah-Hartman co->index = 0;
21329d1a50a2SUwe Kleine-König sport = imx_uart_ports[co->index];
2133ab4382d2SGreg Kroah-Hartman if (sport == NULL)
2134ab4382d2SGreg Kroah-Hartman return -ENODEV;
2135ab4382d2SGreg Kroah-Hartman
21361cf93e0dSHuang Shijie /* For setting the registers, we only need to enable the ipg clock. */
21371cf93e0dSHuang Shijie retval = clk_prepare_enable(sport->clk_ipg);
21381cf93e0dSHuang Shijie if (retval)
21391cf93e0dSHuang Shijie goto error_console;
21401cf93e0dSHuang Shijie
2141ab4382d2SGreg Kroah-Hartman if (options)
2142ab4382d2SGreg Kroah-Hartman uart_parse_options(options, &baud, &parity, &bits, &flow);
2143ab4382d2SGreg Kroah-Hartman else
21449d1a50a2SUwe Kleine-König imx_uart_console_get_options(sport, &baud, &parity, &bits);
2145ab4382d2SGreg Kroah-Hartman
21469d1a50a2SUwe Kleine-König imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2147ab4382d2SGreg Kroah-Hartman
21481cf93e0dSHuang Shijie retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
21491cf93e0dSHuang Shijie
21500c727a42SFabio Estevam if (retval) {
2151e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg);
21520c727a42SFabio Estevam goto error_console;
21530c727a42SFabio Estevam }
21540c727a42SFabio Estevam
2155e67c139cSFugang Duan retval = clk_prepare_enable(sport->clk_per);
21560c727a42SFabio Estevam if (retval)
2157e67c139cSFugang Duan clk_disable_unprepare(sport->clk_ipg);
21581cf93e0dSHuang Shijie
21591cf93e0dSHuang Shijie error_console:
21601cf93e0dSHuang Shijie return retval;
2161ab4382d2SGreg Kroah-Hartman }
2162ab4382d2SGreg Kroah-Hartman
21639768a37cSFrancesco Dolcini static int
imx_uart_console_exit(struct console * co)21649768a37cSFrancesco Dolcini imx_uart_console_exit(struct console *co)
21659768a37cSFrancesco Dolcini {
21669768a37cSFrancesco Dolcini struct imx_port *sport = imx_uart_ports[co->index];
21679768a37cSFrancesco Dolcini
21689768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_per);
21699768a37cSFrancesco Dolcini clk_disable_unprepare(sport->clk_ipg);
21709768a37cSFrancesco Dolcini
21719768a37cSFrancesco Dolcini return 0;
21729768a37cSFrancesco Dolcini }
21739768a37cSFrancesco Dolcini
21749d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver;
21759d1a50a2SUwe Kleine-König static struct console imx_uart_console = {
2176ab4382d2SGreg Kroah-Hartman .name = DEV_NAME,
21779d1a50a2SUwe Kleine-König .write = imx_uart_console_write,
2178ab4382d2SGreg Kroah-Hartman .device = uart_console_device,
21799d1a50a2SUwe Kleine-König .setup = imx_uart_console_setup,
21809768a37cSFrancesco Dolcini .exit = imx_uart_console_exit,
2181ab4382d2SGreg Kroah-Hartman .flags = CON_PRINTBUFFER,
2182ab4382d2SGreg Kroah-Hartman .index = -1,
21839d1a50a2SUwe Kleine-König .data = &imx_uart_uart_driver,
2184ab4382d2SGreg Kroah-Hartman };
2185ab4382d2SGreg Kroah-Hartman
21869d1a50a2SUwe Kleine-König #define IMX_CONSOLE &imx_uart_console
2187913c6c0eSLucas Stach
2188ab4382d2SGreg Kroah-Hartman #else
2189ab4382d2SGreg Kroah-Hartman #define IMX_CONSOLE NULL
2190ab4382d2SGreg Kroah-Hartman #endif
2191ab4382d2SGreg Kroah-Hartman
21929d1a50a2SUwe Kleine-König static struct uart_driver imx_uart_uart_driver = {
2193ab4382d2SGreg Kroah-Hartman .owner = THIS_MODULE,
2194ab4382d2SGreg Kroah-Hartman .driver_name = DRIVER_NAME,
2195ab4382d2SGreg Kroah-Hartman .dev_name = DEV_NAME,
2196ab4382d2SGreg Kroah-Hartman .major = SERIAL_IMX_MAJOR,
2197ab4382d2SGreg Kroah-Hartman .minor = MINOR_START,
21989d1a50a2SUwe Kleine-König .nr = ARRAY_SIZE(imx_uart_ports),
2199ab4382d2SGreg Kroah-Hartman .cons = IMX_CONSOLE,
2200ab4382d2SGreg Kroah-Hartman };
2201ab4382d2SGreg Kroah-Hartman
imx_trigger_start_tx(struct hrtimer * t)2202bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2203cb1a6092SUwe Kleine-König {
2204bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2205cb1a6092SUwe Kleine-König unsigned long flags;
2206cb1a6092SUwe Kleine-König
2207cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags);
2208cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_RTS)
2209cb1a6092SUwe Kleine-König imx_uart_start_tx(&sport->port);
2210cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags);
2211bd78ecd6SAhmad Fatoum
2212bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART;
2213cb1a6092SUwe Kleine-König }
2214cb1a6092SUwe Kleine-König
imx_trigger_stop_tx(struct hrtimer * t)2215bd78ecd6SAhmad Fatoum static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2216cb1a6092SUwe Kleine-König {
2217bd78ecd6SAhmad Fatoum struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2218cb1a6092SUwe Kleine-König unsigned long flags;
2219cb1a6092SUwe Kleine-König
2220cb1a6092SUwe Kleine-König spin_lock_irqsave(&sport->port.lock, flags);
2221cb1a6092SUwe Kleine-König if (sport->tx_state == WAIT_AFTER_SEND)
2222cb1a6092SUwe Kleine-König imx_uart_stop_tx(&sport->port);
2223cb1a6092SUwe Kleine-König spin_unlock_irqrestore(&sport->port.lock, flags);
2224bd78ecd6SAhmad Fatoum
2225bd78ecd6SAhmad Fatoum return HRTIMER_NORESTART;
2226cb1a6092SUwe Kleine-König }
2227cb1a6092SUwe Kleine-König
222800d7a00eSIlpo Järvinen static const struct serial_rs485 imx_rs485_supported = {
222900d7a00eSIlpo Järvinen .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
223000d7a00eSIlpo Järvinen SER_RS485_RX_DURING_TX,
223100d7a00eSIlpo Järvinen .delay_rts_before_send = 1,
223200d7a00eSIlpo Järvinen .delay_rts_after_send = 1,
223300d7a00eSIlpo Järvinen };
223400d7a00eSIlpo Järvinen
2235db0a196bSFabien Lahoudere /* Default RX DMA buffer configuration */
2236db0a196bSFabien Lahoudere #define RX_DMA_PERIODS 16
2237db0a196bSFabien Lahoudere #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2238db0a196bSFabien Lahoudere
imx_uart_probe(struct platform_device * pdev)22399d1a50a2SUwe Kleine-König static int imx_uart_probe(struct platform_device *pdev)
2240ab4382d2SGreg Kroah-Hartman {
22414661f46eSFabio Estevam struct device_node *np = pdev->dev.of_node;
2242ab4382d2SGreg Kroah-Hartman struct imx_port *sport;
2243ab4382d2SGreg Kroah-Hartman void __iomem *base;
2244db0a196bSFabien Lahoudere u32 dma_buf_conf[2];
22454444dcf1SUwe Kleine-König int ret = 0;
224679d0224fSMarek Vasut u32 ucr1, ucr2, uts;
2247ab4382d2SGreg Kroah-Hartman struct resource *res;
2248842633bdSUwe Kleine-König int txirq, rxirq, rtsirq;
2249ab4382d2SGreg Kroah-Hartman
225042d34191SSachin Kamat sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2251ab4382d2SGreg Kroah-Hartman if (!sport)
2252ab4382d2SGreg Kroah-Hartman return -ENOMEM;
2253ab4382d2SGreg Kroah-Hartman
22544661f46eSFabio Estevam sport->devdata = of_device_get_match_data(&pdev->dev);
22554661f46eSFabio Estevam
22564661f46eSFabio Estevam ret = of_alias_get_id(np, "serial");
22574661f46eSFabio Estevam if (ret < 0) {
22584661f46eSFabio Estevam dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
225942d34191SSachin Kamat return ret;
22604661f46eSFabio Estevam }
22614661f46eSFabio Estevam sport->port.line = ret;
22624661f46eSFabio Estevam
2263822a729aSRob Herring sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2264822a729aSRob Herring of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
22654661f46eSFabio Estevam
2266822a729aSRob Herring sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
22674661f46eSFabio Estevam
2268ef194140SRob Herring sport->have_rtsgpio = of_property_present(np, "rts-gpios");
22694661f46eSFabio Estevam
2270822a729aSRob Herring sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
22714661f46eSFabio Estevam
2272822a729aSRob Herring sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
227322698aa2SShawn Guo
2274db0a196bSFabien Lahoudere if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2275db0a196bSFabien Lahoudere sport->rx_period_length = dma_buf_conf[0];
2276db0a196bSFabien Lahoudere sport->rx_periods = dma_buf_conf[1];
2277db0a196bSFabien Lahoudere } else {
2278db0a196bSFabien Lahoudere sport->rx_period_length = RX_DMA_PERIOD_LEN;
2279db0a196bSFabien Lahoudere sport->rx_periods = RX_DMA_PERIODS;
2280db0a196bSFabien Lahoudere }
2281db0a196bSFabien Lahoudere
22829d1a50a2SUwe Kleine-König if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
228356734448SGeert Uytterhoeven dev_err(&pdev->dev, "serial%d out of range\n",
228456734448SGeert Uytterhoeven sport->port.line);
228556734448SGeert Uytterhoeven return -EINVAL;
228656734448SGeert Uytterhoeven }
228756734448SGeert Uytterhoeven
228857c2dab5SYangtao Li base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2289da82f997SAlexander Shiyan if (IS_ERR(base))
2290da82f997SAlexander Shiyan return PTR_ERR(base);
2291ab4382d2SGreg Kroah-Hartman
2292842633bdSUwe Kleine-König rxirq = platform_get_irq(pdev, 0);
2293aa49d8e8SAnson Huang if (rxirq < 0)
2294aa49d8e8SAnson Huang return rxirq;
229531a8d8faSAnson Huang txirq = platform_get_irq_optional(pdev, 1);
229631a8d8faSAnson Huang rtsirq = platform_get_irq_optional(pdev, 2);
2297842633bdSUwe Kleine-König
2298ab4382d2SGreg Kroah-Hartman sport->port.dev = &pdev->dev;
2299ab4382d2SGreg Kroah-Hartman sport->port.mapbase = res->start;
2300ab4382d2SGreg Kroah-Hartman sport->port.membase = base;
23015b109564SZheng Yongjun sport->port.type = PORT_IMX;
2302ab4382d2SGreg Kroah-Hartman sport->port.iotype = UPIO_MEM;
2303842633bdSUwe Kleine-König sport->port.irq = rxirq;
2304ab4382d2SGreg Kroah-Hartman sport->port.fifosize = 32;
2305aa3479d2SDmitry Safonov sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
23069d1a50a2SUwe Kleine-König sport->port.ops = &imx_uart_pops;
23079d1a50a2SUwe Kleine-König sport->port.rs485_config = imx_uart_rs485_config;
230800d7a00eSIlpo Järvinen /* RTS is required to control the RS485 transmitter */
230900d7a00eSIlpo Järvinen if (sport->have_rtscts || sport->have_rtsgpio)
23100139da50SIlpo Järvinen sport->port.rs485_supported = imx_rs485_supported;
2311ab4382d2SGreg Kroah-Hartman sport->port.flags = UPF_BOOT_AUTOCONF;
23129d1a50a2SUwe Kleine-König timer_setup(&sport->timer, imx_uart_timeout, 0);
2313ab4382d2SGreg Kroah-Hartman
231458362d5bSUwe Kleine-König sport->gpios = mctrl_gpio_init(&sport->port, 0);
231558362d5bSUwe Kleine-König if (IS_ERR(sport->gpios))
231658362d5bSUwe Kleine-König return PTR_ERR(sport->gpios);
231758362d5bSUwe Kleine-König
23183a9465faSSascha Hauer sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
23193a9465faSSascha Hauer if (IS_ERR(sport->clk_ipg)) {
23203a9465faSSascha Hauer ret = PTR_ERR(sport->clk_ipg);
2321833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
232242d34191SSachin Kamat return ret;
2323ab4382d2SGreg Kroah-Hartman }
2324ab4382d2SGreg Kroah-Hartman
23253a9465faSSascha Hauer sport->clk_per = devm_clk_get(&pdev->dev, "per");
23263a9465faSSascha Hauer if (IS_ERR(sport->clk_per)) {
23273a9465faSSascha Hauer ret = PTR_ERR(sport->clk_per);
2328833462e9SUwe Kleine-König dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
232942d34191SSachin Kamat return ret;
23303a9465faSSascha Hauer }
23313a9465faSSascha Hauer
23323a9465faSSascha Hauer sport->port.uartclk = clk_get_rate(sport->clk_per);
2333ab4382d2SGreg Kroah-Hartman
23348a61f0c7SFabio Estevam /* For register access, we only need to enable the ipg clock. */
23358a61f0c7SFabio Estevam ret = clk_prepare_enable(sport->clk_ipg);
23361e512d45SUwe Kleine-König if (ret) {
233705ba3df0SChristoph Niedermaier dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
23388a61f0c7SFabio Estevam return ret;
23391e512d45SUwe Kleine-König }
23408a61f0c7SFabio Estevam
2341c150c0f3SLukas Wunner ret = uart_get_rs485_mode(&sport->port);
234245d709f3SChristoph Niedermaier if (ret)
234345d709f3SChristoph Niedermaier goto err_clk;
2344743f93f8SLukas Wunner
23456d215f83SStefan Agner /*
23466d215f83SStefan Agner * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
23476d215f83SStefan Agner * signal cannot be set low during transmission in case the
23486d215f83SStefan Agner * receiver is off (limitation of the i.MX UART IP).
23496d215f83SStefan Agner */
23506d215f83SStefan Agner if (sport->port.rs485.flags & SER_RS485_ENABLED &&
23516d215f83SStefan Agner sport->have_rtscts && !sport->have_rtsgpio &&
23526d215f83SStefan Agner (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
23536d215f83SStefan Agner !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
23546d215f83SStefan Agner dev_err(&pdev->dev,
23556d215f83SStefan Agner "low-active RTS not possible when receiver is off, enabling receiver\n");
23566d215f83SStefan Agner
23578a61f0c7SFabio Estevam /* Disable interrupts before requesting them */
23584444dcf1SUwe Kleine-König ucr1 = imx_uart_readl(sport, UCR1);
23595f0e708cSYe Bin ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
23604444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
23618a61f0c7SFabio Estevam
2362ef25e16eSPeng Fan /* Disable Ageing Timer interrupt */
2363ef25e16eSPeng Fan ucr2 = imx_uart_readl(sport, UCR2);
2364ef25e16eSPeng Fan ucr2 &= ~UCR2_ATEN;
2365ef25e16eSPeng Fan imx_uart_writel(sport, ucr2, UCR2);
2366ef25e16eSPeng Fan
236779d0224fSMarek Vasut /*
236879d0224fSMarek Vasut * In case RS485 is enabled without GPIO RTS control, the UART IP
236979d0224fSMarek Vasut * is used to control CTS signal. Keep both the UART and Receiver
237079d0224fSMarek Vasut * enabled, otherwise the UART IP pulls CTS signal always HIGH no
237179d0224fSMarek Vasut * matter how the UCR2 CTSC and CTS bits are set. To prevent any
237279d0224fSMarek Vasut * data from being fed into the RX FIFO, enable loopback mode in
237379d0224fSMarek Vasut * UTS register, which disconnects the RX path from external RXD
237479d0224fSMarek Vasut * pin and connects it to the Transceiver, which is disabled, so
237579d0224fSMarek Vasut * no data can be fed to the RX FIFO that way.
237679d0224fSMarek Vasut */
237779d0224fSMarek Vasut if (sport->port.rs485.flags & SER_RS485_ENABLED &&
237879d0224fSMarek Vasut sport->have_rtscts && !sport->have_rtsgpio) {
237979d0224fSMarek Vasut uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
238079d0224fSMarek Vasut uts |= UTS_LOOP;
238179d0224fSMarek Vasut imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
238279d0224fSMarek Vasut
238379d0224fSMarek Vasut ucr1 = imx_uart_readl(sport, UCR1);
238479d0224fSMarek Vasut ucr1 |= UCR1_UARTEN;
238579d0224fSMarek Vasut imx_uart_writel(sport, ucr1, UCR1);
238679d0224fSMarek Vasut
238779d0224fSMarek Vasut ucr2 = imx_uart_readl(sport, UCR2);
238879d0224fSMarek Vasut ucr2 |= UCR2_RXEN;
238979d0224fSMarek Vasut imx_uart_writel(sport, ucr2, UCR2);
239079d0224fSMarek Vasut }
239179d0224fSMarek Vasut
23929d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2393e61c38d8SUwe Kleine-König /*
2394e61c38d8SUwe Kleine-König * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2395e61c38d8SUwe Kleine-König * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2396e61c38d8SUwe Kleine-König * and DCD (when they are outputs) or enables the respective
2397e61c38d8SUwe Kleine-König * irqs. So set this bit early, i.e. before requesting irqs.
2398e61c38d8SUwe Kleine-König */
23994444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR);
24004444dcf1SUwe Kleine-König if (!(ufcr & UFCR_DCEDTE))
24014444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2402e61c38d8SUwe Kleine-König
2403e61c38d8SUwe Kleine-König /*
2404e61c38d8SUwe Kleine-König * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2405e61c38d8SUwe Kleine-König * enabled later because they cannot be cleared
2406e61c38d8SUwe Kleine-König * (confirmed on i.MX25) which makes them unusable.
2407e61c38d8SUwe Kleine-König */
240827c84426SUwe Kleine-König imx_uart_writel(sport,
240927c84426SUwe Kleine-König IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
241027c84426SUwe Kleine-König UCR3);
2411e61c38d8SUwe Kleine-König
2412e61c38d8SUwe Kleine-König } else {
24134444dcf1SUwe Kleine-König u32 ucr3 = UCR3_DSR;
24144444dcf1SUwe Kleine-König u32 ufcr = imx_uart_readl(sport, UFCR);
24154444dcf1SUwe Kleine-König if (ufcr & UFCR_DCEDTE)
24164444dcf1SUwe Kleine-König imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
24176df765dcSUwe Kleine-König
24189d1a50a2SUwe Kleine-König if (!imx_uart_is_imx1(sport))
24196df765dcSUwe Kleine-König ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
242027c84426SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3);
2421e61c38d8SUwe Kleine-König }
2422e61c38d8SUwe Kleine-König
2423bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2424bd78ecd6SAhmad Fatoum hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2425bd78ecd6SAhmad Fatoum sport->trigger_start_tx.function = imx_trigger_start_tx;
2426bd78ecd6SAhmad Fatoum sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2427cb1a6092SUwe Kleine-König
2428c0d1c6b0SFabio Estevam /*
2429c0d1c6b0SFabio Estevam * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2430c0d1c6b0SFabio Estevam * chips only have one interrupt.
2431c0d1c6b0SFabio Estevam */
2432842633bdSUwe Kleine-König if (txirq > 0) {
24339d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2434c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport);
24351e512d45SUwe Kleine-König if (ret) {
24361e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request rx irq: %d\n",
24371e512d45SUwe Kleine-König ret);
243845d709f3SChristoph Niedermaier goto err_clk;
24391e512d45SUwe Kleine-König }
2440c0d1c6b0SFabio Estevam
24419d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2442c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport);
24431e512d45SUwe Kleine-König if (ret) {
24441e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request tx irq: %d\n",
24451e512d45SUwe Kleine-König ret);
244645d709f3SChristoph Niedermaier goto err_clk;
24471e512d45SUwe Kleine-König }
24487e620984SUwe Kleine-König
24497e620984SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
24507e620984SUwe Kleine-König dev_name(&pdev->dev), sport);
24517e620984SUwe Kleine-König if (ret) {
24527e620984SUwe Kleine-König dev_err(&pdev->dev, "failed to request rts irq: %d\n",
24537e620984SUwe Kleine-König ret);
245445d709f3SChristoph Niedermaier goto err_clk;
24557e620984SUwe Kleine-König }
2456c0d1c6b0SFabio Estevam } else {
24579d1a50a2SUwe Kleine-König ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2458c0d1c6b0SFabio Estevam dev_name(&pdev->dev), sport);
24591e512d45SUwe Kleine-König if (ret) {
24601e512d45SUwe Kleine-König dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
246145d709f3SChristoph Niedermaier goto err_clk;
2462c0d1c6b0SFabio Estevam }
24631e512d45SUwe Kleine-König }
2464c0d1c6b0SFabio Estevam
24659d1a50a2SUwe Kleine-König imx_uart_ports[sport->port.line] = sport;
2466ab4382d2SGreg Kroah-Hartman
24670a86a86bSRichard Zhao platform_set_drvdata(pdev, sport);
2468ab4382d2SGreg Kroah-Hartman
246945d709f3SChristoph Niedermaier ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
247045d709f3SChristoph Niedermaier
247145d709f3SChristoph Niedermaier err_clk:
247245d709f3SChristoph Niedermaier clk_disable_unprepare(sport->clk_ipg);
247345d709f3SChristoph Niedermaier
247445d709f3SChristoph Niedermaier return ret;
2475ab4382d2SGreg Kroah-Hartman }
2476ab4382d2SGreg Kroah-Hartman
imx_uart_remove(struct platform_device * pdev)24779d1a50a2SUwe Kleine-König static int imx_uart_remove(struct platform_device *pdev)
2478ab4382d2SGreg Kroah-Hartman {
2479ab4382d2SGreg Kroah-Hartman struct imx_port *sport = platform_get_drvdata(pdev);
2480ab4382d2SGreg Kroah-Hartman
2481d5b3d02dSUwe Kleine-König uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2482d5b3d02dSUwe Kleine-König
2483d5b3d02dSUwe Kleine-König return 0;
2484ab4382d2SGreg Kroah-Hartman }
2485ab4382d2SGreg Kroah-Hartman
imx_uart_restore_context(struct imx_port * sport)24869d1a50a2SUwe Kleine-König static void imx_uart_restore_context(struct imx_port *sport)
2487c868cbb7SEduardo Valentin {
248807b5e16eSAnson Huang unsigned long flags;
248907b5e16eSAnson Huang
249007b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags);
249107b5e16eSAnson Huang if (!sport->context_saved) {
249207b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags);
2493c868cbb7SEduardo Valentin return;
249407b5e16eSAnson Huang }
2495c868cbb7SEduardo Valentin
249627c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[4], UFCR);
249727c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[5], UESC);
249827c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[6], UTIM);
249927c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[7], UBIR);
250027c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[8], UBMR);
250127c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
250227c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[0], UCR1);
250327c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
250427c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[2], UCR3);
250527c84426SUwe Kleine-König imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2506c868cbb7SEduardo Valentin sport->context_saved = false;
250707b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags);
2508c868cbb7SEduardo Valentin }
2509c868cbb7SEduardo Valentin
imx_uart_save_context(struct imx_port * sport)25109d1a50a2SUwe Kleine-König static void imx_uart_save_context(struct imx_port *sport)
2511c868cbb7SEduardo Valentin {
251207b5e16eSAnson Huang unsigned long flags;
251307b5e16eSAnson Huang
2514c868cbb7SEduardo Valentin /* Save necessary regs */
251507b5e16eSAnson Huang spin_lock_irqsave(&sport->port.lock, flags);
251627c84426SUwe Kleine-König sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
251727c84426SUwe Kleine-König sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
251827c84426SUwe Kleine-König sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
251927c84426SUwe Kleine-König sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
252027c84426SUwe Kleine-König sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
252127c84426SUwe Kleine-König sport->saved_reg[5] = imx_uart_readl(sport, UESC);
252227c84426SUwe Kleine-König sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
252327c84426SUwe Kleine-König sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
252427c84426SUwe Kleine-König sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
252527c84426SUwe Kleine-König sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2526c868cbb7SEduardo Valentin sport->context_saved = true;
252707b5e16eSAnson Huang spin_unlock_irqrestore(&sport->port.lock, flags);
2528c868cbb7SEduardo Valentin }
2529c868cbb7SEduardo Valentin
imx_uart_enable_wakeup(struct imx_port * sport,bool on)25309d1a50a2SUwe Kleine-König static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2531189550b8SEduardo Valentin {
25324444dcf1SUwe Kleine-König u32 ucr3;
2533189550b8SEduardo Valentin
25344444dcf1SUwe Kleine-König ucr3 = imx_uart_readl(sport, UCR3);
253509df0b34SMartin Kaiser if (on) {
253627c84426SUwe Kleine-König imx_uart_writel(sport, USR1_AWAKE, USR1);
25374444dcf1SUwe Kleine-König ucr3 |= UCR3_AWAKEN;
25384444dcf1SUwe Kleine-König } else {
25394444dcf1SUwe Kleine-König ucr3 &= ~UCR3_AWAKEN;
254009df0b34SMartin Kaiser }
25414444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr3, UCR3);
2542bc85734bSEduardo Valentin
254338b1f0fbSFabio Estevam if (sport->have_rtscts) {
25444444dcf1SUwe Kleine-König u32 ucr1 = imx_uart_readl(sport, UCR1);
2545c67643b4SFugang Duan if (on) {
2546c67643b4SFugang Duan imx_uart_writel(sport, USR1_RTSD, USR1);
25474444dcf1SUwe Kleine-König ucr1 |= UCR1_RTSDEN;
2548c67643b4SFugang Duan } else {
25494444dcf1SUwe Kleine-König ucr1 &= ~UCR1_RTSDEN;
2550c67643b4SFugang Duan }
25514444dcf1SUwe Kleine-König imx_uart_writel(sport, ucr1, UCR1);
2552189550b8SEduardo Valentin }
255338b1f0fbSFabio Estevam }
2554189550b8SEduardo Valentin
imx_uart_suspend_noirq(struct device * dev)25559d1a50a2SUwe Kleine-König static int imx_uart_suspend_noirq(struct device *dev)
255690bb6bd3SShenwei Wang {
2557a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev);
255890bb6bd3SShenwei Wang
25599d1a50a2SUwe Kleine-König imx_uart_save_context(sport);
256090bb6bd3SShenwei Wang
256190bb6bd3SShenwei Wang clk_disable(sport->clk_ipg);
256290bb6bd3SShenwei Wang
2563fcfed1beSAnson Huang pinctrl_pm_select_sleep_state(dev);
2564fcfed1beSAnson Huang
256590bb6bd3SShenwei Wang return 0;
256690bb6bd3SShenwei Wang }
256790bb6bd3SShenwei Wang
imx_uart_resume_noirq(struct device * dev)25689d1a50a2SUwe Kleine-König static int imx_uart_resume_noirq(struct device *dev)
256990bb6bd3SShenwei Wang {
2570a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev);
257190bb6bd3SShenwei Wang int ret;
257290bb6bd3SShenwei Wang
2573fcfed1beSAnson Huang pinctrl_pm_select_default_state(dev);
2574fcfed1beSAnson Huang
257590bb6bd3SShenwei Wang ret = clk_enable(sport->clk_ipg);
257690bb6bd3SShenwei Wang if (ret)
257790bb6bd3SShenwei Wang return ret;
257890bb6bd3SShenwei Wang
25799d1a50a2SUwe Kleine-König imx_uart_restore_context(sport);
258090bb6bd3SShenwei Wang
258190bb6bd3SShenwei Wang return 0;
258290bb6bd3SShenwei Wang }
258390bb6bd3SShenwei Wang
imx_uart_suspend(struct device * dev)25849d1a50a2SUwe Kleine-König static int imx_uart_suspend(struct device *dev)
258590bb6bd3SShenwei Wang {
2586a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev);
258709df0b34SMartin Kaiser int ret;
258890bb6bd3SShenwei Wang
25899d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port);
259081b289ccSMaxim Yu. Osipov disable_irq(sport->port.irq);
259190bb6bd3SShenwei Wang
259209df0b34SMartin Kaiser ret = clk_prepare_enable(sport->clk_ipg);
259309df0b34SMartin Kaiser if (ret)
259409df0b34SMartin Kaiser return ret;
259509df0b34SMartin Kaiser
259609df0b34SMartin Kaiser /* enable wakeup from i.MX UART */
25979d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, true);
259809df0b34SMartin Kaiser
259909df0b34SMartin Kaiser return 0;
260090bb6bd3SShenwei Wang }
260190bb6bd3SShenwei Wang
imx_uart_resume(struct device * dev)26029d1a50a2SUwe Kleine-König static int imx_uart_resume(struct device *dev)
260390bb6bd3SShenwei Wang {
2604a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev);
260590bb6bd3SShenwei Wang
260690bb6bd3SShenwei Wang /* disable wakeup from i.MX UART */
26079d1a50a2SUwe Kleine-König imx_uart_enable_wakeup(sport, false);
260890bb6bd3SShenwei Wang
26099d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port);
261081b289ccSMaxim Yu. Osipov enable_irq(sport->port.irq);
261190bb6bd3SShenwei Wang
261209df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg);
261329add68dSMartin Fuzzey
261490bb6bd3SShenwei Wang return 0;
261590bb6bd3SShenwei Wang }
261690bb6bd3SShenwei Wang
imx_uart_freeze(struct device * dev)26179d1a50a2SUwe Kleine-König static int imx_uart_freeze(struct device *dev)
261894be6d74SPhilipp Zabel {
2619a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev);
262094be6d74SPhilipp Zabel
26219d1a50a2SUwe Kleine-König uart_suspend_port(&imx_uart_uart_driver, &sport->port);
262294be6d74SPhilipp Zabel
262309df0b34SMartin Kaiser return clk_prepare_enable(sport->clk_ipg);
262494be6d74SPhilipp Zabel }
262594be6d74SPhilipp Zabel
imx_uart_thaw(struct device * dev)26269d1a50a2SUwe Kleine-König static int imx_uart_thaw(struct device *dev)
262794be6d74SPhilipp Zabel {
2628a406c4b8SWolfram Sang struct imx_port *sport = dev_get_drvdata(dev);
262994be6d74SPhilipp Zabel
26309d1a50a2SUwe Kleine-König uart_resume_port(&imx_uart_uart_driver, &sport->port);
263194be6d74SPhilipp Zabel
263209df0b34SMartin Kaiser clk_disable_unprepare(sport->clk_ipg);
263394be6d74SPhilipp Zabel
263494be6d74SPhilipp Zabel return 0;
263594be6d74SPhilipp Zabel }
263694be6d74SPhilipp Zabel
26379d1a50a2SUwe Kleine-König static const struct dev_pm_ops imx_uart_pm_ops = {
26389d1a50a2SUwe Kleine-König .suspend_noirq = imx_uart_suspend_noirq,
26399d1a50a2SUwe Kleine-König .resume_noirq = imx_uart_resume_noirq,
26409d1a50a2SUwe Kleine-König .freeze_noirq = imx_uart_suspend_noirq,
26414561d800SShawn Guo .thaw_noirq = imx_uart_resume_noirq,
26429d1a50a2SUwe Kleine-König .restore_noirq = imx_uart_resume_noirq,
26439d1a50a2SUwe Kleine-König .suspend = imx_uart_suspend,
26449d1a50a2SUwe Kleine-König .resume = imx_uart_resume,
26459d1a50a2SUwe Kleine-König .freeze = imx_uart_freeze,
26469d1a50a2SUwe Kleine-König .thaw = imx_uart_thaw,
26479d1a50a2SUwe Kleine-König .restore = imx_uart_thaw,
264890bb6bd3SShenwei Wang };
264990bb6bd3SShenwei Wang
26509d1a50a2SUwe Kleine-König static struct platform_driver imx_uart_platform_driver = {
26519d1a50a2SUwe Kleine-König .probe = imx_uart_probe,
26529d1a50a2SUwe Kleine-König .remove = imx_uart_remove,
2653ab4382d2SGreg Kroah-Hartman
2654ab4382d2SGreg Kroah-Hartman .driver = {
2655ab4382d2SGreg Kroah-Hartman .name = "imx-uart",
265622698aa2SShawn Guo .of_match_table = imx_uart_dt_ids,
26579d1a50a2SUwe Kleine-König .pm = &imx_uart_pm_ops,
2658ab4382d2SGreg Kroah-Hartman },
2659ab4382d2SGreg Kroah-Hartman };
2660ab4382d2SGreg Kroah-Hartman
imx_uart_init(void)26619d1a50a2SUwe Kleine-König static int __init imx_uart_init(void)
2662ab4382d2SGreg Kroah-Hartman {
26639d1a50a2SUwe Kleine-König int ret = uart_register_driver(&imx_uart_uart_driver);
2664ab4382d2SGreg Kroah-Hartman
2665ab4382d2SGreg Kroah-Hartman if (ret)
2666ab4382d2SGreg Kroah-Hartman return ret;
2667ab4382d2SGreg Kroah-Hartman
26689d1a50a2SUwe Kleine-König ret = platform_driver_register(&imx_uart_platform_driver);
2669ab4382d2SGreg Kroah-Hartman if (ret != 0)
26709d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver);
2671ab4382d2SGreg Kroah-Hartman
2672f227824eSUwe Kleine-König return ret;
2673ab4382d2SGreg Kroah-Hartman }
2674ab4382d2SGreg Kroah-Hartman
imx_uart_exit(void)26759d1a50a2SUwe Kleine-König static void __exit imx_uart_exit(void)
2676ab4382d2SGreg Kroah-Hartman {
26779d1a50a2SUwe Kleine-König platform_driver_unregister(&imx_uart_platform_driver);
26789d1a50a2SUwe Kleine-König uart_unregister_driver(&imx_uart_uart_driver);
2679ab4382d2SGreg Kroah-Hartman }
2680ab4382d2SGreg Kroah-Hartman
26819d1a50a2SUwe Kleine-König module_init(imx_uart_init);
26829d1a50a2SUwe Kleine-König module_exit(imx_uart_exit);
2683ab4382d2SGreg Kroah-Hartman
2684ab4382d2SGreg Kroah-Hartman MODULE_AUTHOR("Sascha Hauer");
2685ab4382d2SGreg Kroah-Hartman MODULE_DESCRIPTION("IMX generic serial port driver");
2686ab4382d2SGreg Kroah-Hartman MODULE_LICENSE("GPL");
2687ab4382d2SGreg Kroah-Hartman MODULE_ALIAS("platform:imx-uart");
2688