1c2b39decSFabio Estevam // SPDX-License-Identifier: GPL-2.0+
2c2b39decSFabio Estevam //
3c2b39decSFabio Estevam // i.MX1 pinctrl driver based on imx pinmux core
4c2b39decSFabio Estevam //
5c2b39decSFabio Estevam // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
6edad3b2aSLinus Walleij
74d1db6e7SPaul Gortmaker #include <linux/init.h>
8edad3b2aSLinus Walleij #include <linux/of.h>
9edad3b2aSLinus Walleij #include <linux/platform_device.h>
10edad3b2aSLinus Walleij #include <linux/pinctrl/pinctrl.h>
11edad3b2aSLinus Walleij
12edad3b2aSLinus Walleij #include "pinctrl-imx1.h"
13edad3b2aSLinus Walleij
14edad3b2aSLinus Walleij #define PAD_ID(port, pin) ((port) * 32 + (pin))
15edad3b2aSLinus Walleij #define PA 0
16edad3b2aSLinus Walleij #define PB 1
17edad3b2aSLinus Walleij #define PC 2
18edad3b2aSLinus Walleij #define PD 3
19edad3b2aSLinus Walleij
20edad3b2aSLinus Walleij enum imx1_pads {
21edad3b2aSLinus Walleij MX1_PAD_A24 = PAD_ID(PA, 0),
22edad3b2aSLinus Walleij MX1_PAD_TIN = PAD_ID(PA, 1),
23edad3b2aSLinus Walleij MX1_PAD_PWMO = PAD_ID(PA, 2),
24edad3b2aSLinus Walleij MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
25edad3b2aSLinus Walleij MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
26edad3b2aSLinus Walleij MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
27edad3b2aSLinus Walleij MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
28edad3b2aSLinus Walleij MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
29edad3b2aSLinus Walleij MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
30edad3b2aSLinus Walleij MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
31edad3b2aSLinus Walleij MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
32edad3b2aSLinus Walleij MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
33edad3b2aSLinus Walleij MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
34edad3b2aSLinus Walleij MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
35edad3b2aSLinus Walleij MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
36edad3b2aSLinus Walleij MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
37edad3b2aSLinus Walleij MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
38edad3b2aSLinus Walleij MX1_PAD_DTACK = PAD_ID(PA, 17),
39edad3b2aSLinus Walleij MX1_PAD_BCLK = PAD_ID(PA, 18),
40edad3b2aSLinus Walleij MX1_PAD_LBA = PAD_ID(PA, 19),
41edad3b2aSLinus Walleij MX1_PAD_ECB = PAD_ID(PA, 20),
42edad3b2aSLinus Walleij MX1_PAD_A0 = PAD_ID(PA, 21),
43edad3b2aSLinus Walleij MX1_PAD_CS4 = PAD_ID(PA, 22),
44edad3b2aSLinus Walleij MX1_PAD_CS5 = PAD_ID(PA, 23),
45edad3b2aSLinus Walleij MX1_PAD_A16 = PAD_ID(PA, 24),
46edad3b2aSLinus Walleij MX1_PAD_A17 = PAD_ID(PA, 25),
47edad3b2aSLinus Walleij MX1_PAD_A18 = PAD_ID(PA, 26),
48edad3b2aSLinus Walleij MX1_PAD_A19 = PAD_ID(PA, 27),
49edad3b2aSLinus Walleij MX1_PAD_A20 = PAD_ID(PA, 28),
50edad3b2aSLinus Walleij MX1_PAD_A21 = PAD_ID(PA, 29),
51edad3b2aSLinus Walleij MX1_PAD_A22 = PAD_ID(PA, 30),
52edad3b2aSLinus Walleij MX1_PAD_A23 = PAD_ID(PA, 31),
53edad3b2aSLinus Walleij MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
54edad3b2aSLinus Walleij MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
55edad3b2aSLinus Walleij MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
56edad3b2aSLinus Walleij MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
57edad3b2aSLinus Walleij MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
58edad3b2aSLinus Walleij MX1_PAD_SD_CMD = PAD_ID(PB, 13),
59edad3b2aSLinus Walleij MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
60edad3b2aSLinus Walleij MX1_PAD_SIM_PD = PAD_ID(PB, 15),
61edad3b2aSLinus Walleij MX1_PAD_SIM_TX = PAD_ID(PB, 16),
62edad3b2aSLinus Walleij MX1_PAD_SIM_RX = PAD_ID(PB, 17),
63edad3b2aSLinus Walleij MX1_PAD_SIM_RST = PAD_ID(PB, 18),
64edad3b2aSLinus Walleij MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
65edad3b2aSLinus Walleij MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
66edad3b2aSLinus Walleij MX1_PAD_USBD_OE = PAD_ID(PB, 21),
67edad3b2aSLinus Walleij MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
68edad3b2aSLinus Walleij MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
69edad3b2aSLinus Walleij MX1_PAD_USBD_VP = PAD_ID(PB, 24),
70edad3b2aSLinus Walleij MX1_PAD_USBD_VM = PAD_ID(PB, 25),
71edad3b2aSLinus Walleij MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
72edad3b2aSLinus Walleij MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
73edad3b2aSLinus Walleij MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
74edad3b2aSLinus Walleij MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
75edad3b2aSLinus Walleij MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
76edad3b2aSLinus Walleij MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
77edad3b2aSLinus Walleij MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
78edad3b2aSLinus Walleij MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
79edad3b2aSLinus Walleij MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
80edad3b2aSLinus Walleij MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
81edad3b2aSLinus Walleij MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
82edad3b2aSLinus Walleij MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
83edad3b2aSLinus Walleij MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
84edad3b2aSLinus Walleij MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
85edad3b2aSLinus Walleij MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
86edad3b2aSLinus Walleij MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
87edad3b2aSLinus Walleij MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
88edad3b2aSLinus Walleij MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
89edad3b2aSLinus Walleij MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
90edad3b2aSLinus Walleij MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
91edad3b2aSLinus Walleij MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
92edad3b2aSLinus Walleij MX1_PAD_BT13 = PAD_ID(PC, 19),
93edad3b2aSLinus Walleij MX1_PAD_BT12 = PAD_ID(PC, 20),
94edad3b2aSLinus Walleij MX1_PAD_BT11 = PAD_ID(PC, 21),
95edad3b2aSLinus Walleij MX1_PAD_BT10 = PAD_ID(PC, 22),
96edad3b2aSLinus Walleij MX1_PAD_BT9 = PAD_ID(PC, 23),
97edad3b2aSLinus Walleij MX1_PAD_BT8 = PAD_ID(PC, 24),
98edad3b2aSLinus Walleij MX1_PAD_BT7 = PAD_ID(PC, 25),
99edad3b2aSLinus Walleij MX1_PAD_BT6 = PAD_ID(PC, 26),
100edad3b2aSLinus Walleij MX1_PAD_BT5 = PAD_ID(PC, 27),
101edad3b2aSLinus Walleij MX1_PAD_BT4 = PAD_ID(PC, 28),
102edad3b2aSLinus Walleij MX1_PAD_BT3 = PAD_ID(PC, 29),
103edad3b2aSLinus Walleij MX1_PAD_BT2 = PAD_ID(PC, 30),
104edad3b2aSLinus Walleij MX1_PAD_BT1 = PAD_ID(PC, 31),
105edad3b2aSLinus Walleij MX1_PAD_LSCLK = PAD_ID(PD, 6),
106edad3b2aSLinus Walleij MX1_PAD_REV = PAD_ID(PD, 7),
107edad3b2aSLinus Walleij MX1_PAD_CLS = PAD_ID(PD, 8),
108edad3b2aSLinus Walleij MX1_PAD_PS = PAD_ID(PD, 9),
109edad3b2aSLinus Walleij MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
110edad3b2aSLinus Walleij MX1_PAD_CONTRAST = PAD_ID(PD, 11),
111edad3b2aSLinus Walleij MX1_PAD_ACD_OE = PAD_ID(PD, 12),
112edad3b2aSLinus Walleij MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
113edad3b2aSLinus Walleij MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
114edad3b2aSLinus Walleij MX1_PAD_LD0 = PAD_ID(PD, 15),
115edad3b2aSLinus Walleij MX1_PAD_LD1 = PAD_ID(PD, 16),
116edad3b2aSLinus Walleij MX1_PAD_LD2 = PAD_ID(PD, 17),
117edad3b2aSLinus Walleij MX1_PAD_LD3 = PAD_ID(PD, 18),
118edad3b2aSLinus Walleij MX1_PAD_LD4 = PAD_ID(PD, 19),
119edad3b2aSLinus Walleij MX1_PAD_LD5 = PAD_ID(PD, 20),
120edad3b2aSLinus Walleij MX1_PAD_LD6 = PAD_ID(PD, 21),
121edad3b2aSLinus Walleij MX1_PAD_LD7 = PAD_ID(PD, 22),
122edad3b2aSLinus Walleij MX1_PAD_LD8 = PAD_ID(PD, 23),
123edad3b2aSLinus Walleij MX1_PAD_LD9 = PAD_ID(PD, 24),
124edad3b2aSLinus Walleij MX1_PAD_LD10 = PAD_ID(PD, 25),
125edad3b2aSLinus Walleij MX1_PAD_LD11 = PAD_ID(PD, 26),
126edad3b2aSLinus Walleij MX1_PAD_LD12 = PAD_ID(PD, 27),
127edad3b2aSLinus Walleij MX1_PAD_LD13 = PAD_ID(PD, 28),
128edad3b2aSLinus Walleij MX1_PAD_LD14 = PAD_ID(PD, 29),
129edad3b2aSLinus Walleij MX1_PAD_LD15 = PAD_ID(PD, 30),
130edad3b2aSLinus Walleij MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
131edad3b2aSLinus Walleij };
132edad3b2aSLinus Walleij
133edad3b2aSLinus Walleij /* Pad names for the pinmux subsystem */
134edad3b2aSLinus Walleij static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
135edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A24),
136edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_TIN),
137edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_PWMO),
138edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
139edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
140edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
141edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
142edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
143edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
144edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
145edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
146edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
147edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
148edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
149edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
150edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
151edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
152edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_DTACK),
153edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BCLK),
154edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LBA),
155edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_ECB),
156edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A0),
157edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CS4),
158edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CS5),
159edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A16),
160edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A17),
161edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A18),
162edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A19),
163edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A20),
164edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A21),
165edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A22),
166edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_A23),
167edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
168edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
169edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
170edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
171edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
172edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
173edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
174edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
175edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
176edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
177edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
178edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
179edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
180edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
181edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
182edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
183edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
184edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
185edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
186edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
187edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
188edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
189edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
190edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
191edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
192edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
193edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
194edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
195edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
196edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
197edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
198edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
199edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
200edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
201edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
202edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
203edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
204edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
205edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT13),
206edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT12),
207edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT11),
208edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT10),
209edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT9),
210edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT8),
211edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT7),
212edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT6),
213edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT5),
214edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT4),
215edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT3),
216edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT2),
217edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_BT1),
218edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
219edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_REV),
220edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CLS),
221edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_PS),
222edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
223edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
224edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
225edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
226edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
227edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD0),
228edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD1),
229edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD2),
230edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD3),
231edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD4),
232edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD5),
233edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD6),
234edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD7),
235edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD8),
236edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD9),
237edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD10),
238edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD11),
239edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD12),
240edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD13),
241edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD14),
242edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_LD15),
243edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
244edad3b2aSLinus Walleij };
245edad3b2aSLinus Walleij
246edad3b2aSLinus Walleij static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
247edad3b2aSLinus Walleij .pins = imx1_pinctrl_pads,
248edad3b2aSLinus Walleij .npins = ARRAY_SIZE(imx1_pinctrl_pads),
249edad3b2aSLinus Walleij };
250edad3b2aSLinus Walleij
imx1_pinctrl_probe(struct platform_device * pdev)251edad3b2aSLinus Walleij static int __init imx1_pinctrl_probe(struct platform_device *pdev)
252edad3b2aSLinus Walleij {
253edad3b2aSLinus Walleij return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
254edad3b2aSLinus Walleij }
255edad3b2aSLinus Walleij
256edad3b2aSLinus Walleij static const struct of_device_id imx1_pinctrl_of_match[] = {
257edad3b2aSLinus Walleij { .compatible = "fsl,imx1-iomuxc", },
258edad3b2aSLinus Walleij { }
259edad3b2aSLinus Walleij };
260edad3b2aSLinus Walleij
261edad3b2aSLinus Walleij static struct platform_driver imx1_pinctrl_driver = {
262edad3b2aSLinus Walleij .driver = {
263edad3b2aSLinus Walleij .name = "imx1-pinctrl",
264edad3b2aSLinus Walleij .of_match_table = imx1_pinctrl_of_match,
265*8a83ecd8SFabio Estevam .suppress_bind_attrs = true,
266edad3b2aSLinus Walleij },
267edad3b2aSLinus Walleij };
2684d1db6e7SPaul Gortmaker builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
269