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/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/
H A Dtypes.h21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h23 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
26 823437500, /* 823.4375 MHz PLL */
33 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
36 783360000, /* 783.36 MHz */
43 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
46 796875000, /* 796.875 MHz */
53 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
56 816000000, /* 816 MHz */
63 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
66 830078125, /* 830.78125 MHz */
[all …]
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c36 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
40 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
41 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
42 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
43 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
44 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
45 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
46 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
50 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
55 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
[all …]
/openbmc/u-boot/board/freescale/common/
H A Didt8t49n222a_serdes_clk.c64 debug("Only one refclk at 122.88MHz is not supported." in set_serdes_refclk()
65 " Please set both refclk1 & refclk2 to 122.88MHz" in set_serdes_refclk()
66 " or both not to 122.88MHz.\n"); in set_serdes_refclk()
73 debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
74 " or 156.25MHz.\n"); in set_serdes_refclk()
81 debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" in set_serdes_refclk()
82 " or 156.25MHz.\n"); in set_serdes_refclk()
92 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz in set_serdes_refclk()
117 * Refclk1 = 100MHz Refclk2 = 125MHz in set_serdes_refclk()
125 * Refclk1 = 125MHz Refclk2 = 125MHz in set_serdes_refclk()
[all …]
H A Didt8t49n222a_serdes_clk.h22 SERDES_REFCLK_100, /* refclk 100Mhz */
23 SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
24 SERDES_REFCLK_125, /* refclk 125Mhz */
25 SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
30 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
42 * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
54 * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
63 * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
71 * Refclk1 : 100MHz Refclk2 : 156.25MHz
79 * Refclk1 : 125MHz Refclk2 : 156.25MHz
[all …]
/openbmc/linux/drivers/media/usb/dvb-usb-v2/
H A Daf9035.h81 16384000, /* 16.38 MHz */
82 20480000, /* 20.48 MHz */
83 36000000, /* 36.00 MHz */
84 30000000, /* 30.00 MHz */
85 26000000, /* 26.00 MHz */
86 28000000, /* 28.00 MHz */
87 32000000, /* 32.00 MHz */
88 34000000, /* 34.00 MHz */
89 24000000, /* 24.00 MHz */
90 22000000, /* 22.00 MHz */
[all …]
H A Dmxl111sf-tuner.h16 MXL_IF_LO = 0x00, /* other IF < 9MHz */
18 MXL_IF_4_0 = 0x01, /* 4.0 MHz */
19 MXL_IF_4_5 = 0x02, /* 4.5 MHz */
20 MXL_IF_4_57 = 0x03, /* 4.57 MHz */
21 MXL_IF_5_0 = 0x04, /* 5.0 MHz */
22 MXL_IF_5_38 = 0x05, /* 5.38 MHz */
23 MXL_IF_6_0 = 0x06, /* 6.0 MHz */
24 MXL_IF_6_28 = 0x07, /* 6.28 MHz */
25 MXL_IF_7_2 = 0x08, /* 7.2 MHz */
26 MXL_IF_35_25 = 0x09, /* 35.25 MHz */
[all …]
/openbmc/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c55 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
56 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
57 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
58 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
59 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
60 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
73 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
74 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
75 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
76 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
[all …]
/openbmc/u-boot/board/sunxi/
H A Ddram_timings_sun4i.h4 # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
10 # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
16 # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
28 # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
34 # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
40 # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
46 # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
52 # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
58 # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dlowlevel_init.S208 /* 12MHz */
216 /* 13MHz */
224 /* 19.2MHz */
232 /* 26MHz */
240 /* 38.4MHz */
255 /* 12MHz */
263 /* 13MHz */
271 /* 19.2MHz */
279 /* 26MHz */
287 /* 38.4MHz */
[all …]
/openbmc/linux/Documentation/userspace-api/media/dvb/
H A Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
66 - 8 MHz
[all …]
/openbmc/u-boot/doc/
H A DREADME.Heterogeneous-SoCs90 CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
93 CCB:666.667 MHz,
94 DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
95 CPRI:600 MHz
96 MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
97 FMAN1: 666.667 MHz
98 QMAN: 333.333 MHz
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dtuner-types.c65 { 16 * 140.25 /*MHz*/, 0x8e, 0x02, },
66 { 16 * 463.25 /*MHz*/, 0x8e, 0x04, },
81 { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, },
82 { 16 * 463.25 /*MHz*/, 0x8e, 0x90, },
97 { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, },
98 { 16 * 451.25 /*MHz*/, 0x8e, 0x90, },
114 { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, },
115 { 16 * 447.25 /*MHz*/, 0x8e, 0x97, },
131 { 16 * 168.25 /*MHz*/, 0x8e, 0xa0, },
132 { 16 * 447.25 /*MHz*/, 0x8e, 0x90, },
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h69 #define MHz 1000000 macro
71 #define OSC_HZ (24*MHz)
72 #define LPLL_HZ (600*MHz)
73 #define BPLL_HZ (600*MHz)
74 #define GPLL_HZ (594*MHz)
75 #define CPLL_HZ (384*MHz)
76 #define PPLL_HZ (676*MHz)
78 #define PMU_PCLK_HZ (48*MHz)
80 #define ACLKM_CORE_L_HZ (300*MHz)
81 #define ATCLK_CORE_L_HZ (300*MHz)
[all …]
/openbmc/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
235 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) in rbtx4927_clock_init()
236 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) in rbtx4927_clock_init()
237 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) in rbtx4927_clock_init()
238 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) in rbtx4927_clock_init()
239 * i.e. S9[3]: ON (83MHz), OFF (100MHz) in rbtx4927_clock_init()
245 txx9_cpu_clock = 166666666; /* 166MHz */ in rbtx4927_clock_init()
248 txx9_cpu_clock = 200000000; /* 200MHz */ in rbtx4927_clock_init()
255 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4937_clock_init()
260 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) in rbtx4937_clock_init()
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl12xx/
H A Dwl12xx.h73 WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */
74 WL12XX_REFCLOCK_26 = 1, /* 26 MHz */
75 WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */
76 WL12XX_REFCLOCK_52 = 3, /* 52 MHz */
77 WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */
78 WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */
83 WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */
84 WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */
85 WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */
86 WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */
[all …]

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