| /openbmc/linux/Documentation/arch/arm/stm32/ |
| H A D | overview.rst | 9 Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
15 For MCUs, use the provided default configuration:
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| H A D | stm32f769-overview.rst | 32 …st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32…
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| H A D | stm32f746-overview.rst | 30 …t.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm3…
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| /openbmc/linux/drivers/gpu/drm/stm/ |
| H A D | Kconfig | 13 STMicroelectronics STM32 MCUs.
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| /openbmc/qemu/include/hw/misc/ |
| H A D | stm32l4x5_syscfg.h | 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| H A D | stm32l4x5_exti.h | 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| H A D | stm32l4x5_rcc.h | 13 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/qemu/include/hw/char/ |
| H A D | stm32l4x5_usart.h | 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/qemu/target/avr/ |
| H A D | cpu.c | 253 * This type of AVR core is present in the following AVR MCUs:
295 * This type of AVR core is present in the following AVR MCUs:
326 * This type of AVR core is present in the following AVR MCUs:
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| /openbmc/qemu/include/hw/gpio/ |
| H A D | stm32l4x5_gpio.h | 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/linux/Documentation/devicetree/bindings/input/ |
| H A D | cypress,tm2-touchkey.yaml | 14 Samsung devices. They are implemented using many different MCUs, but use
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| /openbmc/qemu/include/hw/arm/ |
| H A D | stm32l4x5_soc.h | 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | allegro,al5e.yaml | 18 MCUs share an interrupt.
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| /openbmc/qemu/docs/system/arm/ |
| H A D | stm32.rst | 7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
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| /openbmc/linux/drivers/edac/ |
| H A D | xgene_edac.c | 56 struct list_head mcus; member
259 * we must only enable top level interrupt after all MCUs are in xgene_edac_mc_irq_ctl()
263 * MCUs and registered MCUs. in xgene_edac_mc_irq_ctl()
421 list_add(&ctx->next, &edac->mcus); in xgene_edac_mc_add()
1826 list_for_each_entry(mcu, &ctx->mcus, next) in xgene_edac_isr()
1857 INIT_LIST_HEAD(&edac->mcus); in xgene_edac_probe()
1973 list_for_each_entry_safe(mcu, temp_mcu, &edac->mcus, next) in xgene_edac_remove()
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| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | st,stm32-pinctrl.txt | 3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
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| /openbmc/linux/Documentation/arch/arm/ |
| H A D | microchip.rst | 160 * ARM Cortex-M7 MCUs
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| /openbmc/linux/drivers/dma/ |
| H A D | Kconfig | 564 STM32 MCUs.
573 STM32 MCUs.
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | st,stm32-pinctrl.yaml | 14 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
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| /openbmc/linux/drivers/reset/ |
| H A D | Kconfig | 229 - RCC reset controller in STM32 MCUs
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| /openbmc/qemu/hw/misc/ |
| H A D | stm32l4x5_exti.c | 21 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| H A D | stm32l4x5_syscfg.c | 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/qemu/hw/gpio/ |
| H A D | stm32l4x5_gpio.c | 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/qemu/hw/arm/ |
| H A D | stm32l4x5_soc.c | 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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| /openbmc/qemu/hw/char/ |
| H A D | stm32l4x5_usart.c | 15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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