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/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
113 nvidia,lp0-vec:
116 <start length> Starting address and length of LP0 vector.
117 The LP0 vector contains the warm boot code that is executed
118 by AVP when resuming from the LP0 state.
/openbmc/linux/arch/arm/mach-tegra/
H A Dsleep-tegra20.S140 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
267 * puts memory in self-refresh for LP0 and LP1
277 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
323 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
H A Dsleep-tegra30.S37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
281 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
295 * LP0 / LP1 use physical address, since the MMU needs to be
648 * puts memory in self-refresh for LP0 and LP1
658 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
745 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
H A Dpm.c261 * copy these code to IRAM before LP0/LP1 suspend and restore the content
343 [TEGRA_SUSPEND_LP0] = "LP0",
418 "self-refresh -- LP0/LP1 unavailable\n", in tegra_pm_init_suspend()
H A Dreset-handler.S29 * an LP2 transition. Also branched to by LP0 and LP1 resume after
/openbmc/linux/Documentation/admin-guide/
H A Dparport.rst221 Both the above examples would inform lp that you want ``/dev/lp0`` to be
226 name, so ``/dev/lp0`` was always the port at 0x3bc. This is no longer the
227 case - if you only have one port, it will default to being ``/dev/lp0``,
H A Dserial-console.rst25 lp0 for the first parallel port
H A Ddevices.txt167 0 = /dev/lp0 Parallel printer on parport0
975 0 = /dev/pd_bdm0 PD BDM interface on lp0
978 4 = /dev/icd_bdm0 ICD BDM interface on lp0
2454 0 = /dev/usb/lp0 First USB printer
/openbmc/u-boot/include/configs/
H A Dseaboard.h12 /* LP0 suspend / resume */
/openbmc/linux/arch/arm/include/asm/mach/
H A Darch.h40 unsigned char reserve_lp0 :1; /* never has lp0 */
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c139 * use when returning from LP0 for PLL stabilization delays. in wb_start()
/openbmc/linux/drivers/char/
H A Dlp.c44 * lp=parport1,none,parport2 (bind lp0 to parport1, disable lp1 and
71 * lp0 0x3bc
77 * to lp0 regardless of its I/O address. If you need the old behaviour, you
H A DKconfig68 option "console=lp0" to the kernel at boot time.
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c2552 * and thus fail gracefully if LP0 watermarks in ilk_validate_wm_level()
2649 /* ILK primary LP0 latency is 700 ns */ in ilk_read_wm_latency()
2658 /* ILK sprite LP0 latency is 1300 ns */ in intel_fixup_spr_wm_latency()
2666 /* ILK cursor LP0 latency is 1300 ns */ in intel_fixup_cur_wm_latency()
2767 /* LP0 watermark maximums depend on this pipe alone */ in ilk_validate_pipe_wm()
2775 /* LP0 watermarks always use 1/2 DDB partitioning */ in ilk_validate_pipe_wm()
2778 /* At least LP0 must be valid */ in ilk_validate_pipe_wm()
2780 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n"); in ilk_validate_pipe_wm()
3069 /* LP0 register values */ in ilk_compute_wm_results()
3360 * For active pipes LP0 watermark is marked as in ilk_pipe_wm_get_hw_state()
/openbmc/linux/arch/arm/kernel/
H A Dsetup.c209 #define lp0 io_res[0] macro
921 * possessing lp0, lp1 or lp2 in request_standard_resources()
924 request_resource(&ioport_resource, &lp0); in request_standard_resources()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dboard2.c169 /* prepare the WB code to LP0 location */ in board_init()
/openbmc/linux/drivers/soc/tegra/
H A Dregulators-tegra30.c372 * hardware for resuming from LP0. in tegra30_regulator_prepare_suspend()
H A Dregulators-tegra20.c387 * hardware for resuming from LP0. in tegra20_regulator_prepare_suspend()
H A Dpmc.c67 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
374 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
410 * @lp0_vec_phys: physical base address of the LP0 warm boot code
411 * @lp0_vec_size: size of the LP0 warm boot code
1925 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
3366 "LP0"
3720 "LP0",
/openbmc/linux/Documentation/usb/
H A Dgadget-testing.rst891 If udev is active, then e.g. /dev/usb/lp0 should appear.
901 # cat > /dev/usb/lp0
909 # cat /dev/usb/lp0
/openbmc/linux/drivers/ata/
H A Dahci_tegra.c616 /* LP0 suspend support not implemented */
/openbmc/u-boot/drivers/dma/
H A Dbcm6348-iudma.c6 * Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan.dtsi745 vdd_3v3_lp0: regulator-lp0 {
H A Dtegra124-venice2.dts1195 vdd_3v3_lp0: regulator-lp0 {
/openbmc/linux/drivers/scsi/isci/
H A Dport_config.c153 * hardware. The SCU hardware allows for port configurations as follows. LP0

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