1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2ee4bbbcbSTom Warren /* 3ee4bbbcbSTom Warren * (C) Copyright 2010,2011 4ee4bbbcbSTom Warren * NVIDIA Corporation <www.nvidia.com> 5ee4bbbcbSTom Warren */ 6ee4bbbcbSTom Warren 7ee4bbbcbSTom Warren #ifndef __CONFIG_H 8ee4bbbcbSTom Warren #define __CONFIG_H 9ee4bbbcbSTom Warren 101ace4022SAlexey Brodkin #include <linux/sizes.h> 11649d0ffbSSimon Glass 12649d0ffbSSimon Glass /* LP0 suspend / resume */ 1329f3e3f2STom Warren #define CONFIG_TEGRA_LP0 14649d0ffbSSimon Glass #define CONFIG_TEGRA_PMU 15649d0ffbSSimon Glass #define CONFIG_TPS6586X_POWER 16649d0ffbSSimon Glass #define CONFIG_TEGRA_CLOCK_SCALING 17649d0ffbSSimon Glass 1800a2749dSAllen Martin #include "tegra20-common.h" 19ee4bbbcbSTom Warren 20ee4bbbcbSTom Warren /* High-level configuration options */ 2129f3e3f2STom Warren #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" 22ee4bbbcbSTom Warren 23ee4bbbcbSTom Warren /* Board-specific serial config */ 2429f3e3f2STom Warren #define CONFIG_TEGRA_ENABLE_UARTD 25ee4bbbcbSTom Warren #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE 26ee4bbbcbSTom Warren 2705858736STom Warren #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD 28ee4bbbcbSTom Warren 29f9f2f12eSStephen Warren /* Environment in eMMC, at the end of 2nd "boot sector" */ 3091171091SStephen Warren #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 31f9f2f12eSStephen Warren #define CONFIG_SYS_MMC_ENV_DEV 0 32573668a2SStephen Warren #define CONFIG_SYS_MMC_ENV_PART 2 33db44ebdbSSimon Glass 340dd84084SSimon Glass /* NAND support */ 350dd84084SSimon Glass #define CONFIG_TEGRA_NAND 360dd84084SSimon Glass 370dd84084SSimon Glass /* Max number of NAND devices */ 380dd84084SSimon Glass #define CONFIG_SYS_MAX_NAND_DEVICE 1 39ef24c38aSSimon Glass 40ef24c38aSSimon Glass #include "tegra-common-post.h" 41ef24c38aSSimon Glass 42ee4bbbcbSTom Warren #endif /* __CONFIG_H */ 43