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/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml4 $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
13 LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
23 - qcom,sc7180-llcc
24 - qcom,sc7280-llcc
25 - qcom,sc8180x-llcc
26 - qcom,sc8280xp-llcc
27 - qcom,sdm845-llcc
28 - qcom,sm6350-llcc
29 - qcom,sm7150-llcc
30 - qcom,sm8150-llcc
[all …]
/openbmc/linux/include/linux/soc/qcom/
H A Dllcc-qcom.h61 * @slice_id: llcc slice id
62 * @slice_size: Size allocated for the llcc slice
70 * struct llcc_edac_reg_data - llcc edac registers data for each error type
88 /* LLCC TRP registers */
98 /* LLCC Common registers */
103 /* LLCC DRP registers */
116 * struct llcc_drv_data - Data associated with the llcc driver
117 * @regmaps: regmaps associated with the llcc device
118 * @bcast_regmap: regmap associated with llcc broadcast offset
120 * @edac_reg_offset: Offset of the LLCC EDAC registers
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8998-bwmon.yaml20 (DDR) - called LLCC BWMON.
32 - qcom,sm6350-llcc-bwmon
38 - qcom,sc7180-llcc-bwmon
39 - qcom,sc8280xp-llcc-bwmon
41 - qcom,sm8250-llcc-bwmon
42 - qcom,sm8550-llcc-bwmon
43 - const: qcom,sc7280-llcc-bwmon
44 - const: qcom,sc7280-llcc-bwmon # BWMON v5
45 - const: qcom,sdm845-llcc-bwmon # BWMON v5
/openbmc/linux/drivers/soc/qcom/
H A Dllcc-qcom.c19 #include <linux/soc/qcom/llcc-qcom.h>
69 * struct llcc_slice_config - Data associated with the llcc slice
71 * @slice_id: llcc slice id for each client
85 * When configured to 0 all ways in llcc are probed.
369 /* LLCC Common registers */
374 /* LLCC DRP registers */
396 /* LLCC Common registers */
401 /* LLCC DRP registers */
413 /* LLCC register offset starting from v1.0.0 */
419 /* LLCC register offset starting from v2.0.1 */
[all …]
H A DKconfig64 tristate "Qualcomm Technologies, Inc. LLCC driver"
69 Last Level Cache Controller(LLCC) driver for platforms such as,
70 SDM845. This provides interfaces to clients that use the LLCC.
71 Say yes here to enable LLCC slice driver.
H A DMakefile30 obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
H A Dicc-bwmon.c854 { .compatible = "qcom,sdm845-llcc-bwmon", .data = &sdm845_llcc_bwmon_data },
855 { .compatible = "qcom,sc7280-llcc-bwmon", .data = &sc7280_llcc_bwmon_data },
/openbmc/linux/drivers/edac/
H A Dqcom_edac.c12 #include <linux/soc/qcom/llcc-qcom.h>
265 "LLCC Data RAM correctable Error"); in dump_syn_reg()
269 "LLCC Data RAM uncorrectable Error"); in dump_syn_reg()
273 "LLCC Tag RAM correctable Error"); in dump_syn_reg()
277 "LLCC Tag RAM uncorrectable Error"); in dump_syn_reg()
350 edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank", in qcom_llcc_edac_probe()
361 edev_ctl->ctl_name = "llcc"; in qcom_llcc_edac_probe()
364 /* Check if LLCC driver has passed ECC IRQ */ in qcom_llcc_edac_probe()
H A DKconfig516 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dqcom-soc.yaml18 qcom,sdm845-llcc-bwmon
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_6_9_sm6375.h118 .min_llcc_ib = 0, /* No LLCC on this SoC */
H A Ddpu_5_4_sm6125.h172 .min_llcc_ib = 0, /* No LLCC on this SoC */
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.h194 * @bw_split_vote : true if bw controlled by llcc/dram bw properties
H A Ddpu_hw_catalog.h734 * @min_llcc_ib minimum llcc ib vote in kbps
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm850-samsung-w737.dts394 &llcc {
H A Dsm6350.dtsi1711 compatible = "qcom,sm6350-llcc";
1731 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1770 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
H A Dsc7180.dtsi2862 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2915 compatible = "qcom,sc7180-llcc";
H A Dqdu1000.dtsi1447 compatible = "qcom,qdu1000-llcc";
H A Dsm8550.dtsi3851 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3944 compatible = "qcom,sm8550-llcc";
H A Dsdm845.dtsi2219 llcc: system-cache-controller@1100000 { label
2220 compatible = "qcom,sdm845-llcc";
2236 compatible = "qcom,sdm845-llcc-bwmon";
H A Dsc8280xp.dtsi3240 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3331 compatible = "qcom,sc8280xp-llcc";
H A Dsm8250.dtsi3681 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3879 compatible = "qcom,sm8250-llcc";
H A Dsc7280.dtsi3507 compatible = "qcom,sc7280-llcc-bwmon";
3597 compatible = "qcom,sc7280-llcc";
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c14 #include <linux/soc/qcom/llcc-qcom.h>
1808 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_destroy()
1821 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ in a6xx_llc_slices_init()
/openbmc/linux/drivers/net/ethernet/sun/
H A Dcassini.h2200 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP, \
2298 { "LLCc?",0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S3_CLNP,
2378 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,
2434 { "LLCc?", 0xff00, 0x0300, OP_EQ, 2, S1_IPV4, 0, S1_CLNP,

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