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/openbmc/linux/drivers/clk/starfive/
H A DKconfig25 bool "StarFive JH7110 PLL clock support"
30 StarFive JH7110 SoC.
33 bool "StarFive JH7110 system clock support"
42 StarFive JH7110 SoC.
45 tristate "StarFive JH7110 always-on clock support"
50 StarFive JH7110 SoC.
53 tristate "StarFive JH7110 System-Top-Group clock support"
58 on the StarFive JH7110 SoC.
61 tristate "StarFive JH7110 Image-Signal-Process clock support"
66 on the StarFive JH7110 SoC.
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H A DMakefile7 obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
8 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
9 obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
10 obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
11 obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
12 obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
H A Dclk-starfive-jh7110-aon.c3 * StarFive JH7110 Always-On Clock Driver
13 #include <dt-bindings/clock/starfive,jh7110-crg.h>
15 #include "clk-starfive-jh7110.h"
138 { .compatible = "starfive,jh7110-aoncrg" },
146 .name = "clk-starfive-jh7110-aon",
153 MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
/openbmc/linux/Documentation/devicetree/bindings/soc/starfive/
H A Dstarfive,jh7110-syscon.yaml4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
7 title: StarFive JH7110 SoC system controller
13 The StarFive JH7110 SoC system controller provides register information such
20 - const: starfive,jh7110-sys-syscon
25 - starfive,jh7110-aon-syscon
26 - starfive,jh7110-stg-syscon
33 $ref: /schemas/clock/starfive,jh7110-pll.yaml#
48 const: starfive,jh7110-sys-syscon
59 const: starfive,jh7110-aon-syscon
72 compatible = "starfive,jh7110-stg-syscon", "syscon";
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-voutcrg.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
14 const: starfive,jh7110-voutcrg
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
70 #include <dt-bindings/clock/starfive,jh7110-crg.h>
71 #include <dt-bindings/power/starfive,jh7110-pmu.h>
72 #include <dt-bindings/reset/starfive,jh7110-crg.h>
75 compatible = "starfive,jh7110-voutcrg";
H A Dstarfive,jh7110-ispcrg.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
14 const: starfive,jh7110-ispcrg
42 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
47 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
68 #include <dt-bindings/clock/starfive,jh7110-crg.h>
69 #include <dt-bindings/power/starfive,jh7110-pmu.h>
70 #include <dt-bindings/reset/starfive,jh7110-crg.h>
73 compatible = "starfive,jh7110-ispcrg";
H A Dstarfive,jh7110-stgcrg.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
14 const: starfive,jh7110-stgcrg
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
66 compatible = "starfive,jh7110-stgcrg";
H A Dstarfive,jh7110-pll.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
22 const: starfive,jh7110-pll
31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
43 compatible = "starfive,jh7110-pll";
H A Dstarfive,jh7110-aoncrg.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
14 const: starfive,jh7110-aoncrg
71 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
76 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
90 #include <dt-bindings/clock/starfive,jh7110-crg.h>
93 compatible = "starfive,jh7110-aoncrg";
H A Dstarfive,jh7110-syscrg.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
7 title: StarFive JH7110 System Clock and Reset Generator
14 const: starfive,jh7110-syscrg
82 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
87 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
102 compatible = "starfive,jh7110-syscrg";
/openbmc/linux/drivers/crypto/starfive/
H A DMakefile3 obj-$(CONFIG_CRYPTO_DEV_JH7110) += jh7110-crypto.o
4 jh7110-crypto-objs := jh7110-cryp.o jh7110-hash.o jh7110-rsa.o jh7110-aes.o
/openbmc/linux/drivers/phy/starfive/
H A DKconfig9 tristate "StarFive JH7110 D-PHY RX support"
16 phy-jh7110-dphy-rx.ko.
19 tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
26 phy-jh7110-pcie.ko.
29 tristate "Starfive JH7110 USB 2.0 PHY support"
36 phy-jh7110-usb.ko.
H A DMakefile2 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) += phy-jh7110-dphy-rx.o
3 obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
4 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
/openbmc/linux/Documentation/devicetree/bindings/power/
H A Dstarfive,jh7110-pmu.yaml4 $id: http://devicetree.org/schemas/power/starfive,jh7110-pmu.yaml#
7 title: StarFive JH7110 Power Management Unit
13 StarFive JH7110 SoC includes support for multiple power domains which can be
19 - starfive,jh7110-pmu
41 compatible = "starfive,jh7110-pmu";
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
14 compatible = "starfive,jh7110";
340 compatible = "starfive,jh7110-clint", "sifive,clint0";
350 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
361 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
495 compatible = "starfive,jh7110-tdm";
516 compatible = "starfive,jh7110-usb";
548 compatible = "starfive,jh7110-usb-phy";
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dstarfive,jh7110-tdm.yaml4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-tdm.yaml#
7 title: StarFive JH7110 TDM Controller
11 integrated in StarFive JH7110 SoC, allowing up to 8 channels of
24 - starfive,jh7110-tdm
81 compatible = "starfive,jh7110-tdm";
H A Dsnps,designware-i2s.yaml20 - starfive,jh7110-i2stx0
21 - starfive,jh7110-i2stx1
22 - starfive,jh7110-i2srx
126 const: starfive,jh7110-i2stx0
141 const: starfive,jh7110-i2stx1
156 const: starfive,jh7110-i2srx
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dstarfive,jh7110-usb-phy.yaml4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
7 title: StarFive JH7110 USB 2.0 PHY
14 const: starfive,jh7110-usb-phy
44 compatible = "starfive,jh7110-usb-phy";
H A Dstarfive,jh7110-dphy-rx.yaml4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
19 const: starfive,jh7110-dphy-rx
61 compatible = "starfive,jh7110-dphy-rx";
H A Dstarfive,jh7110-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
7 title: StarFive JH7110 PCIe 2.0 PHY
14 const: starfive,jh7110-pcie-phy
53 compatible = "starfive,jh7110-pcie-phy";
/openbmc/linux/drivers/pinctrl/starfive/
H A DKconfig30 tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC"
36 Say yes here to support system pin control on the StarFive JH7110 SoC.
42 tristate "Always-on pinctrl and GPIO driver for the StarFive JH7110 SoC"
48 Say yes here to support always-on pin control on the StarFive JH7110 SoC.
H A Dpinctrl-starfive-jh7110-aon.c3 * Pinctrl / GPIO driver for StarFive JH7110 SoC aon controller
24 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
29 #include "pinctrl-starfive-jh7110.h"
159 .compatible = "starfive,jh7110-aon-pinctrl",
169 .name = "starfive-jh7110-aon-pinctrl",
176 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC aon controller");
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dstarfive,jh7110-aon-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
7 title: StarFive JH7110 AON Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
22 const: starfive,jh7110-aon-pinctrl
103 compatible = "starfive,jh7110-aon-pinctrl";
H A Dstarfive,jh7110-sys-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
7 title: StarFive JH7110 SYS Pin Controller
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
25 const: starfive,jh7110-sys-pinctrl
111 compatible = "starfive,jh7110-sys-pinctrl";
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml7 title: StarFive Watchdog for JH7100 and JH7110 SoC
14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
15 has only one timeout phase and reboots. And JH7110 watchdog has two
29 - starfive,jh7110-wdt

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