1*9b3938c0SXingyu Wu# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*9b3938c0SXingyu Wu%YAML 1.2 3*9b3938c0SXingyu Wu--- 4*9b3938c0SXingyu Wu$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml# 5*9b3938c0SXingyu Wu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*9b3938c0SXingyu Wu 7*9b3938c0SXingyu Wutitle: StarFive JH7110 Image-Signal-Process Clock and Reset Generator 8*9b3938c0SXingyu Wu 9*9b3938c0SXingyu Wumaintainers: 10*9b3938c0SXingyu Wu - Xingyu Wu <xingyu.wu@starfivetech.com> 11*9b3938c0SXingyu Wu 12*9b3938c0SXingyu Wuproperties: 13*9b3938c0SXingyu Wu compatible: 14*9b3938c0SXingyu Wu const: starfive,jh7110-ispcrg 15*9b3938c0SXingyu Wu 16*9b3938c0SXingyu Wu reg: 17*9b3938c0SXingyu Wu maxItems: 1 18*9b3938c0SXingyu Wu 19*9b3938c0SXingyu Wu clocks: 20*9b3938c0SXingyu Wu items: 21*9b3938c0SXingyu Wu - description: ISP Top core 22*9b3938c0SXingyu Wu - description: ISP Top Axi 23*9b3938c0SXingyu Wu - description: NOC ISP Bus 24*9b3938c0SXingyu Wu - description: external DVP 25*9b3938c0SXingyu Wu 26*9b3938c0SXingyu Wu clock-names: 27*9b3938c0SXingyu Wu items: 28*9b3938c0SXingyu Wu - const: isp_top_core 29*9b3938c0SXingyu Wu - const: isp_top_axi 30*9b3938c0SXingyu Wu - const: noc_bus_isp_axi 31*9b3938c0SXingyu Wu - const: dvp_clk 32*9b3938c0SXingyu Wu 33*9b3938c0SXingyu Wu resets: 34*9b3938c0SXingyu Wu items: 35*9b3938c0SXingyu Wu - description: ISP Top core 36*9b3938c0SXingyu Wu - description: ISP Top Axi 37*9b3938c0SXingyu Wu - description: NOC ISP Bus 38*9b3938c0SXingyu Wu 39*9b3938c0SXingyu Wu '#clock-cells': 40*9b3938c0SXingyu Wu const: 1 41*9b3938c0SXingyu Wu description: 42*9b3938c0SXingyu Wu See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. 43*9b3938c0SXingyu Wu 44*9b3938c0SXingyu Wu '#reset-cells': 45*9b3938c0SXingyu Wu const: 1 46*9b3938c0SXingyu Wu description: 47*9b3938c0SXingyu Wu See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. 48*9b3938c0SXingyu Wu 49*9b3938c0SXingyu Wu power-domains: 50*9b3938c0SXingyu Wu maxItems: 1 51*9b3938c0SXingyu Wu description: 52*9b3938c0SXingyu Wu ISP domain power 53*9b3938c0SXingyu Wu 54*9b3938c0SXingyu Wurequired: 55*9b3938c0SXingyu Wu - compatible 56*9b3938c0SXingyu Wu - reg 57*9b3938c0SXingyu Wu - clocks 58*9b3938c0SXingyu Wu - clock-names 59*9b3938c0SXingyu Wu - resets 60*9b3938c0SXingyu Wu - '#clock-cells' 61*9b3938c0SXingyu Wu - '#reset-cells' 62*9b3938c0SXingyu Wu - power-domains 63*9b3938c0SXingyu Wu 64*9b3938c0SXingyu WuadditionalProperties: false 65*9b3938c0SXingyu Wu 66*9b3938c0SXingyu Wuexamples: 67*9b3938c0SXingyu Wu - | 68*9b3938c0SXingyu Wu #include <dt-bindings/clock/starfive,jh7110-crg.h> 69*9b3938c0SXingyu Wu #include <dt-bindings/power/starfive,jh7110-pmu.h> 70*9b3938c0SXingyu Wu #include <dt-bindings/reset/starfive,jh7110-crg.h> 71*9b3938c0SXingyu Wu 72*9b3938c0SXingyu Wu ispcrg: clock-controller@19810000 { 73*9b3938c0SXingyu Wu compatible = "starfive,jh7110-ispcrg"; 74*9b3938c0SXingyu Wu reg = <0x19810000 0x10000>; 75*9b3938c0SXingyu Wu clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, 76*9b3938c0SXingyu Wu <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, 77*9b3938c0SXingyu Wu <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, 78*9b3938c0SXingyu Wu <&dvp_clk>; 79*9b3938c0SXingyu Wu clock-names = "isp_top_core", "isp_top_axi", 80*9b3938c0SXingyu Wu "noc_bus_isp_axi", "dvp_clk"; 81*9b3938c0SXingyu Wu resets = <&syscrg JH7110_SYSRST_ISP_TOP>, 82*9b3938c0SXingyu Wu <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, 83*9b3938c0SXingyu Wu <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; 84*9b3938c0SXingyu Wu #clock-cells = <1>; 85*9b3938c0SXingyu Wu #reset-cells = <1>; 86*9b3938c0SXingyu Wu power-domains = <&pwrc JH7110_PD_ISP>; 87*9b3938c0SXingyu Wu }; 88