1*a097a5ecSXingyu Wu# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2*a097a5ecSXingyu Wu%YAML 1.2
3*a097a5ecSXingyu Wu---
4*a097a5ecSXingyu Wu$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
5*a097a5ecSXingyu Wu$schema: http://devicetree.org/meta-schemas/core.yaml#
6*a097a5ecSXingyu Wu
7*a097a5ecSXingyu Wutitle: StarFive JH7110 Video-Output Clock and Reset Generator
8*a097a5ecSXingyu Wu
9*a097a5ecSXingyu Wumaintainers:
10*a097a5ecSXingyu Wu  - Xingyu Wu <xingyu.wu@starfivetech.com>
11*a097a5ecSXingyu Wu
12*a097a5ecSXingyu Wuproperties:
13*a097a5ecSXingyu Wu  compatible:
14*a097a5ecSXingyu Wu    const: starfive,jh7110-voutcrg
15*a097a5ecSXingyu Wu
16*a097a5ecSXingyu Wu  reg:
17*a097a5ecSXingyu Wu    maxItems: 1
18*a097a5ecSXingyu Wu
19*a097a5ecSXingyu Wu  clocks:
20*a097a5ecSXingyu Wu    items:
21*a097a5ecSXingyu Wu      - description: Vout Top core
22*a097a5ecSXingyu Wu      - description: Vout Top Ahb
23*a097a5ecSXingyu Wu      - description: Vout Top Axi
24*a097a5ecSXingyu Wu      - description: Vout Top HDMI MCLK
25*a097a5ecSXingyu Wu      - description: I2STX0 BCLK
26*a097a5ecSXingyu Wu      - description: external HDMI pixel
27*a097a5ecSXingyu Wu
28*a097a5ecSXingyu Wu  clock-names:
29*a097a5ecSXingyu Wu    items:
30*a097a5ecSXingyu Wu      - const: vout_src
31*a097a5ecSXingyu Wu      - const: vout_top_ahb
32*a097a5ecSXingyu Wu      - const: vout_top_axi
33*a097a5ecSXingyu Wu      - const: vout_top_hdmitx0_mclk
34*a097a5ecSXingyu Wu      - const: i2stx0_bclk
35*a097a5ecSXingyu Wu      - const: hdmitx0_pixelclk
36*a097a5ecSXingyu Wu
37*a097a5ecSXingyu Wu  resets:
38*a097a5ecSXingyu Wu    maxItems: 1
39*a097a5ecSXingyu Wu    description: Vout Top core
40*a097a5ecSXingyu Wu
41*a097a5ecSXingyu Wu  '#clock-cells':
42*a097a5ecSXingyu Wu    const: 1
43*a097a5ecSXingyu Wu    description:
44*a097a5ecSXingyu Wu      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
45*a097a5ecSXingyu Wu
46*a097a5ecSXingyu Wu  '#reset-cells':
47*a097a5ecSXingyu Wu    const: 1
48*a097a5ecSXingyu Wu    description:
49*a097a5ecSXingyu Wu      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
50*a097a5ecSXingyu Wu
51*a097a5ecSXingyu Wu  power-domains:
52*a097a5ecSXingyu Wu    maxItems: 1
53*a097a5ecSXingyu Wu    description:
54*a097a5ecSXingyu Wu      Vout domain power
55*a097a5ecSXingyu Wu
56*a097a5ecSXingyu Wurequired:
57*a097a5ecSXingyu Wu  - compatible
58*a097a5ecSXingyu Wu  - reg
59*a097a5ecSXingyu Wu  - clocks
60*a097a5ecSXingyu Wu  - clock-names
61*a097a5ecSXingyu Wu  - resets
62*a097a5ecSXingyu Wu  - '#clock-cells'
63*a097a5ecSXingyu Wu  - '#reset-cells'
64*a097a5ecSXingyu Wu  - power-domains
65*a097a5ecSXingyu Wu
66*a097a5ecSXingyu WuadditionalProperties: false
67*a097a5ecSXingyu Wu
68*a097a5ecSXingyu Wuexamples:
69*a097a5ecSXingyu Wu  - |
70*a097a5ecSXingyu Wu    #include <dt-bindings/clock/starfive,jh7110-crg.h>
71*a097a5ecSXingyu Wu    #include <dt-bindings/power/starfive,jh7110-pmu.h>
72*a097a5ecSXingyu Wu    #include <dt-bindings/reset/starfive,jh7110-crg.h>
73*a097a5ecSXingyu Wu
74*a097a5ecSXingyu Wu    voutcrg: clock-controller@295C0000 {
75*a097a5ecSXingyu Wu        compatible = "starfive,jh7110-voutcrg";
76*a097a5ecSXingyu Wu        reg = <0x295C0000 0x10000>;
77*a097a5ecSXingyu Wu        clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
78*a097a5ecSXingyu Wu                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
79*a097a5ecSXingyu Wu                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
80*a097a5ecSXingyu Wu                 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
81*a097a5ecSXingyu Wu                 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
82*a097a5ecSXingyu Wu                 <&hdmitx0_pixelclk>;
83*a097a5ecSXingyu Wu        clock-names = "vout_src", "vout_top_ahb",
84*a097a5ecSXingyu Wu                      "vout_top_axi", "vout_top_hdmitx0_mclk",
85*a097a5ecSXingyu Wu                      "i2stx0_bclk", "hdmitx0_pixelclk";
86*a097a5ecSXingyu Wu        resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
87*a097a5ecSXingyu Wu        #clock-cells = <1>;
88*a097a5ecSXingyu Wu        #reset-cells = <1>;
89*a097a5ecSXingyu Wu        power-domains = <&pwrc JH7110_PD_VOUT>;
90*a097a5ecSXingyu Wu    };
91