1*ae07a9a8SChanghuang Liang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*ae07a9a8SChanghuang Liang%YAML 1.2
3*ae07a9a8SChanghuang Liang---
4*ae07a9a8SChanghuang Liang$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5*ae07a9a8SChanghuang Liang$schema: http://devicetree.org/meta-schemas/core.yaml#
6*ae07a9a8SChanghuang Liang
7*ae07a9a8SChanghuang Liangtitle: StarFive SoC JH7110 MIPI D-PHY Rx Controller
8*ae07a9a8SChanghuang Liang
9*ae07a9a8SChanghuang Liangmaintainers:
10*ae07a9a8SChanghuang Liang  - Jack Zhu <jack.zhu@starfivetech.com>
11*ae07a9a8SChanghuang Liang  - Changhuang Liang <changhuang.liang@starfivetech.com>
12*ae07a9a8SChanghuang Liang
13*ae07a9a8SChanghuang Liangdescription:
14*ae07a9a8SChanghuang Liang  StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
15*ae07a9a8SChanghuang Liang  transfer CSI camera data.
16*ae07a9a8SChanghuang Liang
17*ae07a9a8SChanghuang Liangproperties:
18*ae07a9a8SChanghuang Liang  compatible:
19*ae07a9a8SChanghuang Liang    const: starfive,jh7110-dphy-rx
20*ae07a9a8SChanghuang Liang
21*ae07a9a8SChanghuang Liang  reg:
22*ae07a9a8SChanghuang Liang    maxItems: 1
23*ae07a9a8SChanghuang Liang
24*ae07a9a8SChanghuang Liang  clocks:
25*ae07a9a8SChanghuang Liang    items:
26*ae07a9a8SChanghuang Liang      - description: config clock
27*ae07a9a8SChanghuang Liang      - description: reference clock
28*ae07a9a8SChanghuang Liang      - description: escape mode transmit clock
29*ae07a9a8SChanghuang Liang
30*ae07a9a8SChanghuang Liang  clock-names:
31*ae07a9a8SChanghuang Liang    items:
32*ae07a9a8SChanghuang Liang      - const: cfg
33*ae07a9a8SChanghuang Liang      - const: ref
34*ae07a9a8SChanghuang Liang      - const: tx
35*ae07a9a8SChanghuang Liang
36*ae07a9a8SChanghuang Liang  resets:
37*ae07a9a8SChanghuang Liang    items:
38*ae07a9a8SChanghuang Liang      - description: DPHY_HW reset
39*ae07a9a8SChanghuang Liang      - description: DPHY_B09_ALWAYS_ON reset
40*ae07a9a8SChanghuang Liang
41*ae07a9a8SChanghuang Liang  power-domains:
42*ae07a9a8SChanghuang Liang    maxItems: 1
43*ae07a9a8SChanghuang Liang
44*ae07a9a8SChanghuang Liang  "#phy-cells":
45*ae07a9a8SChanghuang Liang    const: 0
46*ae07a9a8SChanghuang Liang
47*ae07a9a8SChanghuang Liangrequired:
48*ae07a9a8SChanghuang Liang  - compatible
49*ae07a9a8SChanghuang Liang  - reg
50*ae07a9a8SChanghuang Liang  - clocks
51*ae07a9a8SChanghuang Liang  - clock-names
52*ae07a9a8SChanghuang Liang  - resets
53*ae07a9a8SChanghuang Liang  - power-domains
54*ae07a9a8SChanghuang Liang  - "#phy-cells"
55*ae07a9a8SChanghuang Liang
56*ae07a9a8SChanghuang LiangadditionalProperties: false
57*ae07a9a8SChanghuang Liang
58*ae07a9a8SChanghuang Liangexamples:
59*ae07a9a8SChanghuang Liang  - |
60*ae07a9a8SChanghuang Liang    phy@19820000 {
61*ae07a9a8SChanghuang Liang      compatible = "starfive,jh7110-dphy-rx";
62*ae07a9a8SChanghuang Liang      reg = <0x19820000 0x10000>;
63*ae07a9a8SChanghuang Liang      clocks = <&ispcrg 3>,
64*ae07a9a8SChanghuang Liang               <&ispcrg 4>,
65*ae07a9a8SChanghuang Liang               <&ispcrg 5>;
66*ae07a9a8SChanghuang Liang      clock-names = "cfg", "ref", "tx";
67*ae07a9a8SChanghuang Liang      resets = <&ispcrg 2>,
68*ae07a9a8SChanghuang Liang               <&ispcrg 3>;
69*ae07a9a8SChanghuang Liang      power-domains = <&aon_syscon 1>;
70*ae07a9a8SChanghuang Liang      #phy-cells = <0>;
71*ae07a9a8SChanghuang Liang    };
72