| /openbmc/linux/drivers/media/pci/cx23885/ |
| H A D | altera-ci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * altera-ci.c
5 * CI driver in conjunction with NetUp Dual DVB-T/C RF CI card
13 * GPIO-0 ~INT in
14 * GPIO-1 TMS out
15 * GPIO-2 ~reset chips out
16 * GPIO-3 to GPIO-10 data/addr for CA in/out
17 * GPIO-11 ~CS out
18 * GPIO-12 AD_RG out
19 * GPIO-13 ~WR out
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| /openbmc/linux/Documentation/devicetree/bindings/powerpc/nintendo/ |
| H A D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
46 Represents the "Flipper" interrupt controller within the "Hollywood" chip.
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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| /openbmc/linux/include/linux/usb/ |
| H A D | isp116x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Board initialization code should put one of these into dev->platform_data
13 /* On-chip overcurrent detection */
25 /* Inter-io delay (ns). The chip is picky about access timings; it
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| H A D | isp1362.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * board initialization code should put one of these into dev->platform_data
15 /* On-chip overcurrent protection */
25 /* chip can be resumed via H_WAKEUP pin */
37 /* Inter-io delay (ns). The chip is picky about access timings; it
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| /openbmc/qemu/docs/system/arm/ |
| H A D | stm32.rst | 1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
10 based on this chip :
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
15 based on this chip :
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
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| /openbmc/linux/drivers/mailbox/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
16 Apple SoCs have various co-processors required for certain
70 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
96 This driver provides support for inter-processor communication
184 module will be called mailbox-mpfs.
193 providing an interface for invoking the inter-process communication
206 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
209 An implementation of the APM X-Gene Interprocessor Communication
210 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | sama5d2.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Chip-specific header file for the SAMA5D2 SoC
29 #define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */
30 #define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */
32 #define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
45 #define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */
69 #define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
70 #define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */
91 #define ATMEL_ID_RXLP 76 /* UART Low-Power */
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
36 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
38 serial is specified and High-Speed Inter-Chip feature if HSIC is
44 maximum-speed:
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| /openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/ |
| H A D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
30 +-----+ +---------+ +-------+
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| /openbmc/u-boot/board/mini-box/picosam9g45/ |
| H A D | picosam9g45.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
4 * (C) Copyright 2015 Inter Act B.V.
7 * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
8 * (C) Copyright 2007-2008
29 #include <asm/mach-types.h>
33 /* ------------------------------------------------------------------------- */
51 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
53 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
58 ddr2->rtr = 0x24b; in ddr2_conf()
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| /openbmc/linux/Documentation/arch/loongarch/ |
| H A D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 IRQ chip model (hierarchy) of LoongArch
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
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| /openbmc/linux/Documentation/userspace-api/media/ |
| H A D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
87 Also known as chip.
113 - :term:`CEC API`;
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| /openbmc/linux/arch/arm/mach-shmobile/ |
| H A D | pm-rcar-gen2.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 Power management support
5 * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
18 #include "rcar-gen2.h"
33 #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
35 #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
37 /* On-chip RAM */
38 #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
60 if (of_device_is_compatible(np, "arm,cortex-a15")) in rcar_gen2_pm_init()
62 else if (of_device_is_compatible(np, "arm,cortex-a7")) in rcar_gen2_pm_init()
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| /openbmc/linux/drivers/net/ethernet/apple/ |
| H A D | bmac.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * mace.h - definitions for the registers in the "Big Mac"
17 #define XIFC 0x000 /* low-level interface control */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
41 #define CHIPID 0x170 /* chip ID */
48 #define STATUS 0x200 /* status--reading this clears it */
53 # define RxAlignCntExp 0x00000004 /* Align-error counter expired */
54 # define RxCRCCntExp 0x00000008 /* CRC-error counter expired */
55 # define RxLenCntExp 0x00000010 /* Length-error counter expired */
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| /openbmc/linux/arch/powerpc/platforms/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
37 bool "ePAPR para-virtualization support"
39 Enables ePAPR para-virtualization support for guests.
48 a hypervisor. This option is not user-selectable but should
65 bool "Device-tree based CPU feature discovery & setup"
101 chip, but it can potentially support other global timers
124 registers are used for inter-processor communication.
206 bool "On-chip CPU temperature sensor support"
209 G3 and G4 processors have an on-chip temperature sensor called the
210 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
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| /openbmc/linux/Documentation/devicetree/bindings/display/ |
| H A D | st,stih4xx.txt | 3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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| /openbmc/linux/sound/soc/atmel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Atmel System-on-Chip"
31 in PDC mode configured using audio-graph-card in device-tree.
40 in DMA mode configured using audio-graph-card in device-tree.
43 tristate "SoC Audio support for WM8731-based At91sam9g20 evaluation board"
49 Say Y if you want to add support for SoC audio on WM8731-based
63 tristate "SoC Audio support for WM8731-based at91sam9x5 board"
91 tristate "ASoC driver for the Axentia TSE-850"
98 Axentia TSE-850 with a PCM5142 codec.
110 tristate "Support for Mikroe-PROTO board"
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| /openbmc/linux/drivers/net/ethernet/seeq/ |
| H A D | sgiseeq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
77 #define SEEQ_TCMD_RB1 0x20 /* Register bank one w/multi-cast low byte */
78 #define SEEQ_TCMD_RB2 0x40 /* Register bank two w/multi-cast high byte */
98 #define SEEQ_HCTL_IPEND 0x00000002 /* IRQ is pending for the chip */
99 #define SEEQ_HCTL_IPG 0x00001000 /* Inter-packet gap */
100 #define SEEQ_HCTL_RFIX 0x00002000 /* At rxdc, clear end-of-packet */
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| /openbmc/qemu/hw/sh4/ |
| H A D | sh7750_regs.h | 2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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| /openbmc/linux/drivers/mfd/ |
| H A D | si476x-cmd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mfd/si476x-cmd.c -- Subroutines implementing command
21 #include <linux/mfd/si476x-core.h>
177 if (core->revision != SI476X_REVISION_A10) { in si476x_core_parse_and_nag_about_error()
184 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
188 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
192 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
196 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
200 err = -EINVAL; in si476x_core_parse_and_nag_about_error()
203 cause = "Chip is busy"; in si476x_core_parse_and_nag_about_error()
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| /openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | common.c | 1 // SPDX-License-Identifier: ISC
22 #include "chip.h"
68 MODULE_PARM_DESC(iapp, "Enable partial support for the obsoleted Inter-Access Point Protocol");
82 struct brcmf_pub *drvr = ifp->drvr; in brcmf_c_set_joinpref_default()
109 dload_buf->flag = cpu_to_le16(flag); in brcmf_c_download()
110 dload_buf->dload_type = cpu_to_le16(DL_TYPE_CLM); in brcmf_c_download()
111 dload_buf->len = cpu_to_le32(len); in brcmf_c_download()
112 dload_buf->crc = cpu_to_le32(0); in brcmf_c_download()
124 struct brcmf_pub *drvr = ifp->drvr; in brcmf_c_download_blob()
138 err = -ENOMEM; in brcmf_c_download_blob()
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| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-loongson-eiointc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
82 /* EIO node 0 is in charge of inter-node interrupt dispatch */ in eiointc_set_irq_route()
97 struct eiointc_priv *priv = d->domain->host_data; in eiointc_set_irq_affinity()
102 cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map); in eiointc_set_irq_affinity()
106 return -EINVAL; in eiointc_set_irq_affinity()
110 vector = d->hwirq; in eiointc_set_irq_affinity()
115 0x0, priv->node * CORES_PER_EIO_NODE); in eiointc_set_irq_affinity()
118 eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map); in eiointc_set_irq_affinity()
122 0x0, priv->node * CORES_PER_EIO_NODE); in eiointc_set_irq_affinity()
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-usb | 10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-usb@vger.kernel.org
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-usb@vger.kernel.org
72 extra bus folder "usb-serial" in sysfs; apart from that
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
141 attribute allows user-space to know whether the device is
145 an on-screen keyboard if the only wireless keyboard is
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| /openbmc/linux/sound/soc/tegra/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SoC Audio for the Tegra System-on-Chip"
82 Config to enable the Inter-IC Sound (I2S) Controller which
83 implements full-duplex and bidirectional and single direction
84 point-to-point serial interfaces. It can interface with I2S
113 converts the multi-bit Pulse Code Modulation (PCM) audio input to
114 oversampled 1-bit Pulse Density Modulation (PDM) output. From the
116 that up-samples the input to the desired sampling rate by
118 the desired 1-bit output via Delta Sigma Modulation (DSM).
138 per-stream volume control or for master volume control.
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