1efdbd734SRob HerringSTMicroelectronics stih4xx platforms 2efdbd734SRob Herring 3efdbd734SRob Herring- sti-vtg: video timing generator 4efdbd734SRob Herring Required properties: 5efdbd734SRob Herring - compatible: "st,vtg" 6efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 7efdbd734SRob Herring Optional properties: 8efdbd734SRob Herring - interrupts : VTG interrupt number to the CPU. 9efdbd734SRob Herring - st,slave: phandle on a slave vtg 10efdbd734SRob Herring 11efdbd734SRob Herring- sti-vtac: video timing advanced inter dye communication Rx and TX 12efdbd734SRob Herring Required properties: 13efdbd734SRob Herring - compatible: "st,vtac-main" or "st,vtac-aux" 14efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 15efdbd734SRob Herring - clocks: from common clock binding: handle hardware IP needed clocks, the 16efdbd734SRob Herring number of clocks may depend of the SoC type. 17efdbd734SRob Herring See ../clocks/clock-bindings.txt for details. 18efdbd734SRob Herring - clock-names: names of the clocks listed in clocks property in the same 19efdbd734SRob Herring order. 20efdbd734SRob Herring 21efdbd734SRob Herring- sti-display-subsystem: Master device for DRM sub-components 22efdbd734SRob Herring This device must be the parent of all the sub-components and is responsible 23efdbd734SRob Herring of bind them. 24efdbd734SRob Herring Required properties: 25efdbd734SRob Herring - compatible: "st,sti-display-subsystem" 26efdbd734SRob Herring - ranges: to allow probing of subdevices 27efdbd734SRob Herring 28efdbd734SRob Herring- sti-compositor: frame compositor engine 29efdbd734SRob Herring must be a child of sti-display-subsystem 30efdbd734SRob Herring Required properties: 31efdbd734SRob Herring - compatible: "st,stih<chip>-compositor" 32efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 33efdbd734SRob Herring - clocks: from common clock binding: handle hardware IP needed clocks, the 34efdbd734SRob Herring number of clocks may depend of the SoC type. 35efdbd734SRob Herring See ../clocks/clock-bindings.txt for details. 36efdbd734SRob Herring - clock-names: names of the clocks listed in clocks property in the same 37efdbd734SRob Herring order. 38efdbd734SRob Herring - resets: resets to be used by the device 39efdbd734SRob Herring See ../reset/reset.txt for details. 40efdbd734SRob Herring - reset-names: names of the resets listed in resets property in the same 41efdbd734SRob Herring order. 42efdbd734SRob Herring - st,vtg: phandle(s) on vtg device (main and aux) nodes. 43efdbd734SRob Herring 44efdbd734SRob Herring- sti-tvout: video out hardware block 45efdbd734SRob Herring must be a child of sti-display-subsystem 46efdbd734SRob Herring Required properties: 47efdbd734SRob Herring - compatible: "st,stih<chip>-tvout" 48efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 49efdbd734SRob Herring - reg-names: names of the mapped memory regions listed in regs property in 50efdbd734SRob Herring the same order. 51efdbd734SRob Herring - resets: resets to be used by the device 52efdbd734SRob Herring See ../reset/reset.txt for details. 53efdbd734SRob Herring - reset-names: names of the resets listed in resets property in the same 54efdbd734SRob Herring order. 55efdbd734SRob Herring 56efdbd734SRob Herring- sti-hdmi: hdmi output block 57efdbd734SRob Herring must be a child of sti-display-subsystem 58efdbd734SRob Herring Required properties: 59efdbd734SRob Herring - compatible: "st,stih<chip>-hdmi"; 60efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 61efdbd734SRob Herring - reg-names: names of the mapped memory regions listed in regs property in 62efdbd734SRob Herring the same order. 63efdbd734SRob Herring - interrupts : HDMI interrupt number to the CPU. 64f92ce761SRob Herring - interrupt-names: names of the interrupts listed in interrupts property in 65efdbd734SRob Herring the same order 66efdbd734SRob Herring - clocks: from common clock binding: handle hardware IP needed clocks, the 67efdbd734SRob Herring number of clocks may depend of the SoC type. 68efdbd734SRob Herring - clock-names: names of the clocks listed in clocks property in the same 69efdbd734SRob Herring order. 70efdbd734SRob Herring - ddc: phandle of an I2C controller used for DDC EDID probing 71efdbd734SRob Herring 72efdbd734SRob Herringsti-hda: 73efdbd734SRob Herring Required properties: 74efdbd734SRob Herring must be a child of sti-display-subsystem 75efdbd734SRob Herring - compatible: "st,stih<chip>-hda" 76efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 77efdbd734SRob Herring - reg-names: names of the mapped memory regions listed in regs property in 78efdbd734SRob Herring the same order. 79efdbd734SRob Herring - clocks: from common clock binding: handle hardware IP needed clocks, the 80efdbd734SRob Herring number of clocks may depend of the SoC type. 81efdbd734SRob Herring See ../clocks/clock-bindings.txt for details. 82efdbd734SRob Herring - clock-names: names of the clocks listed in clocks property in the same 83efdbd734SRob Herring order. 84efdbd734SRob Herring 85efdbd734SRob Herringsti-dvo: 86efdbd734SRob Herring Required properties: 87efdbd734SRob Herring must be a child of sti-display-subsystem 88efdbd734SRob Herring - compatible: "st,stih<chip>-dvo" 89efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 90efdbd734SRob Herring - reg-names: names of the mapped memory regions listed in regs property in 91efdbd734SRob Herring the same order. 92efdbd734SRob Herring - clocks: from common clock binding: handle hardware IP needed clocks, the 93efdbd734SRob Herring number of clocks may depend of the SoC type. 94efdbd734SRob Herring See ../clocks/clock-bindings.txt for details. 95efdbd734SRob Herring - clock-names: names of the clocks listed in clocks property in the same 96efdbd734SRob Herring order. 97efdbd734SRob Herring - pinctrl-0: pin control handle 98f92ce761SRob Herring - pinctrl-names: names of the pin control states to use 99efdbd734SRob Herring - sti,panel: phandle of the panel connected to the DVO output 100efdbd734SRob Herring 101efdbd734SRob Herringsti-hqvdp: 102efdbd734SRob Herring must be a child of sti-display-subsystem 103efdbd734SRob Herring Required properties: 104efdbd734SRob Herring - compatible: "st,stih<chip>-hqvdp" 105efdbd734SRob Herring - reg: Physical base address of the IP registers and length of memory mapped region. 106efdbd734SRob Herring - clocks: from common clock binding: handle hardware IP needed clocks, the 107efdbd734SRob Herring number of clocks may depend of the SoC type. 108efdbd734SRob Herring See ../clocks/clock-bindings.txt for details. 109efdbd734SRob Herring - clock-names: names of the clocks listed in clocks property in the same 110efdbd734SRob Herring order. 111efdbd734SRob Herring - resets: resets to be used by the device 112efdbd734SRob Herring See ../reset/reset.txt for details. 113efdbd734SRob Herring - reset-names: names of the resets listed in resets property in the same 114efdbd734SRob Herring order. 115efdbd734SRob Herring - st,vtg: phandle on vtg main device node. 116efdbd734SRob Herring 117efdbd734SRob HerringExample: 118efdbd734SRob Herring 119efdbd734SRob Herring/ { 120efdbd734SRob Herring ... 121efdbd734SRob Herring 122afc3bca4SRob Herring vtg_main_slave: sti-vtg-main-slave@fe85a800 { 123efdbd734SRob Herring compatible = "st,vtg"; 124efdbd734SRob Herring reg = <0xfe85A800 0x300>; 125efdbd734SRob Herring interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>; 126efdbd734SRob Herring }; 127efdbd734SRob Herring 128efdbd734SRob Herring vtg_main: sti-vtg-main-master@fd348000 { 129efdbd734SRob Herring compatible = "st,vtg"; 130efdbd734SRob Herring reg = <0xfd348000 0x400>; 131efdbd734SRob Herring st,slave = <&vtg_main_slave>; 132efdbd734SRob Herring }; 133efdbd734SRob Herring 134efdbd734SRob Herring vtg_aux_slave: sti-vtg-aux-slave@fd348400 { 135efdbd734SRob Herring compatible = "st,vtg"; 136efdbd734SRob Herring reg = <0xfe858200 0x300>; 137efdbd734SRob Herring interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>; 138efdbd734SRob Herring }; 139efdbd734SRob Herring 140efdbd734SRob Herring vtg_aux: sti-vtg-aux-master@fd348400 { 141efdbd734SRob Herring compatible = "st,vtg"; 142efdbd734SRob Herring reg = <0xfd348400 0x400>; 143efdbd734SRob Herring st,slave = <&vtg_aux_slave>; 144efdbd734SRob Herring }; 145efdbd734SRob Herring 146efdbd734SRob Herring 147efdbd734SRob Herring sti-vtac-rx-main@fee82800 { 148efdbd734SRob Herring compatible = "st,vtac-main"; 149efdbd734SRob Herring reg = <0xfee82800 0x200>; 150efdbd734SRob Herring clock-names = "vtac"; 151efdbd734SRob Herring clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>; 152efdbd734SRob Herring }; 153efdbd734SRob Herring 154efdbd734SRob Herring sti-vtac-rx-aux@fee82a00 { 155efdbd734SRob Herring compatible = "st,vtac-aux"; 156efdbd734SRob Herring reg = <0xfee82a00 0x200>; 157efdbd734SRob Herring clock-names = "vtac"; 158efdbd734SRob Herring clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>; 159efdbd734SRob Herring }; 160efdbd734SRob Herring 161efdbd734SRob Herring sti-vtac-tx-main@fd349000 { 162efdbd734SRob Herring compatible = "st,vtac-main"; 163efdbd734SRob Herring reg = <0xfd349000 0x200>, <0xfd320000 0x10000>; 164efdbd734SRob Herring clock-names = "vtac"; 165efdbd734SRob Herring clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; 166efdbd734SRob Herring }; 167efdbd734SRob Herring 168efdbd734SRob Herring sti-vtac-tx-aux@fd349200 { 169efdbd734SRob Herring compatible = "st,vtac-aux"; 170efdbd734SRob Herring reg = <0xfd349200 0x200>, <0xfd320000 0x10000>; 171efdbd734SRob Herring clock-names = "vtac"; 172efdbd734SRob Herring clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; 173efdbd734SRob Herring }; 174efdbd734SRob Herring 175efdbd734SRob Herring sti-display-subsystem { 176efdbd734SRob Herring compatible = "st,sti-display-subsystem"; 177efdbd734SRob Herring ranges; 178efdbd734SRob Herring 179efdbd734SRob Herring sti-compositor@fd340000 { 180efdbd734SRob Herring compatible = "st,stih416-compositor"; 181efdbd734SRob Herring reg = <0xfd340000 0x1000>; 182efdbd734SRob Herring clock-names = "compo_main", "compo_aux", 183efdbd734SRob Herring "pix_main", "pix_aux"; 184efdbd734SRob Herring clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>, 185efdbd734SRob Herring <&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>; 186efdbd734SRob Herring reset-names = "compo-main", "compo-aux"; 187efdbd734SRob Herring resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>; 188efdbd734SRob Herring st,vtg = <&vtg_main>, <&vtg_aux>; 189efdbd734SRob Herring }; 190efdbd734SRob Herring 191efdbd734SRob Herring sti-tvout@fe000000 { 192efdbd734SRob Herring compatible = "st,stih416-tvout"; 193efdbd734SRob Herring reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>; 194efdbd734SRob Herring reg-names = "tvout-reg", "hda-reg", "syscfg"; 195efdbd734SRob Herring reset-names = "tvout"; 196efdbd734SRob Herring resets = <&softreset STIH416_HDTVOUT_SOFTRESET>; 197efdbd734SRob Herring }; 198efdbd734SRob Herring 199efdbd734SRob Herring sti-hdmi@fe85c000 { 200efdbd734SRob Herring compatible = "st,stih416-hdmi"; 201efdbd734SRob Herring reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>; 202efdbd734SRob Herring reg-names = "hdmi-reg", "syscfg"; 203efdbd734SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>; 204efdbd734SRob Herring interrupt-names = "irq"; 205efdbd734SRob Herring clock-names = "pix", "tmds", "phy", "audio"; 206efdbd734SRob Herring clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>; 207efdbd734SRob Herring }; 208efdbd734SRob Herring 209efdbd734SRob Herring sti-hda@fe85a000 { 210efdbd734SRob Herring compatible = "st,stih416-hda"; 211efdbd734SRob Herring reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>; 212efdbd734SRob Herring reg-names = "hda-reg", "video-dacs-ctrl"; 213efdbd734SRob Herring clock-names = "pix", "hddac"; 214efdbd734SRob Herring clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; 215efdbd734SRob Herring }; 216efdbd734SRob Herring 217efdbd734SRob Herring sti-dvo@8d00400 { 218efdbd734SRob Herring compatible = "st,stih407-dvo"; 219efdbd734SRob Herring reg = <0x8d00400 0x200>; 220efdbd734SRob Herring reg-names = "dvo-reg"; 221efdbd734SRob Herring clock-names = "dvo_pix", "dvo", 222efdbd734SRob Herring "main_parent", "aux_parent"; 223efdbd734SRob Herring clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>, 224efdbd734SRob Herring <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; 225efdbd734SRob Herring pinctrl-names = "default"; 226efdbd734SRob Herring pinctrl-0 = <&pinctrl_dvo>; 227efdbd734SRob Herring sti,panel = <&panel_dvo>; 228efdbd734SRob Herring }; 229efdbd734SRob Herring 230efdbd734SRob Herring sti-hqvdp@9c000000 { 231efdbd734SRob Herring compatible = "st,stih407-hqvdp"; 232efdbd734SRob Herring reg = <0x9C00000 0x100000>; 233efdbd734SRob Herring clock-names = "hqvdp", "pix_main"; 234efdbd734SRob Herring clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; 235efdbd734SRob Herring reset-names = "hqvdp"; 236efdbd734SRob Herring resets = <&softreset STIH407_HDQVDP_SOFTRESET>; 237efdbd734SRob Herring st,vtg = <&vtg_main>; 238efdbd734SRob Herring }; 239efdbd734SRob Herring }; 240efdbd734SRob Herring ... 241efdbd734SRob Herring}; 242