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/openbmc/linux/drivers/net/wireless/ti/wl12xx/
H A Ddebugfs.c35 WL12XX_DEBUGFS_FWSTATS_FILE(isr, cmd_cmplt, "%u");
36 WL12XX_DEBUGFS_FWSTATS_FILE(isr, fiqs, "%u");
37 WL12XX_DEBUGFS_FWSTATS_FILE(isr, rx_headers, "%u");
38 WL12XX_DEBUGFS_FWSTATS_FILE(isr, rx_mem_overflow, "%u");
39 WL12XX_DEBUGFS_FWSTATS_FILE(isr, rx_rdys, "%u");
40 WL12XX_DEBUGFS_FWSTATS_FILE(isr, irqs, "%u");
41 WL12XX_DEBUGFS_FWSTATS_FILE(isr, tx_procs, "%u");
42 WL12XX_DEBUGFS_FWSTATS_FILE(isr, decrypt_done, "%u");
43 WL12XX_DEBUGFS_FWSTATS_FILE(isr, dma0_done, "%u");
44 WL12XX_DEBUGFS_FWSTATS_FILE(isr, dma1_done, "%u");
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl1251/
H A Ddebugfs.c117 DEBUGFS_FWSTATS_FILE(isr, cmd_cmplt, 20, "%u");
118 DEBUGFS_FWSTATS_FILE(isr, fiqs, 20, "%u");
119 DEBUGFS_FWSTATS_FILE(isr, rx_headers, 20, "%u");
120 DEBUGFS_FWSTATS_FILE(isr, rx_mem_overflow, 20, "%u");
121 DEBUGFS_FWSTATS_FILE(isr, rx_rdys, 20, "%u");
122 DEBUGFS_FWSTATS_FILE(isr, irqs, 20, "%u");
123 DEBUGFS_FWSTATS_FILE(isr, tx_procs, 20, "%u");
124 DEBUGFS_FWSTATS_FILE(isr, decrypt_done, 20, "%u");
125 DEBUGFS_FWSTATS_FILE(isr, dma0_done, 20, "%u");
126 DEBUGFS_FWSTATS_FILE(isr, dma1_done, 20, "%u");
[all …]
/openbmc/linux/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c15 * There is ISR pseudo-cause register,
17 * Its bits represents OR'ed bits from 3 real ISR registers:
24 * real ISR registers, or hardware may malfunction.
288 u32 isr; in wil6210_irq_rx() local
293 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
297 trace_wil6210_irq_rx(isr); in wil6210_irq_rx()
298 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx()
300 if (unlikely(!isr)) { in wil6210_irq_rx()
312 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE | in wil6210_irq_rx()
314 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n", in wil6210_irq_rx()
[all …]
H A DKconfig20 bool "Use Clear-On-Read mode for ISR registers for wil6210"
24 ISR registers on wil6210 chip may operate in either
28 For ISR debug, use W1C (say n); is allows to monitor ISR
29 registers with debugfs. If COR were used, ISR would
/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c114 REG32(ISR, 0x1C)
116 FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */
117 FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */
118 FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
119 FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
120 FIELD(ISR, SBKF, 18, 1) /* Send break flag */
121 FIELD(ISR, CMF, 17, 1) /* Character match flag */
122 FIELD(ISR, BUSY, 16, 1) /* Busy flag */
123 FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */
124 FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */
[all …]
H A Dipoctal232.c114 uint8_t isr; member
151 VMSTATE_UINT8(isr, SCC2698Block),
186 if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) { in update_irq()
212 blk->isr |= ISR_TXRDY(channel); in write_cr()
217 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
236 blk->isr &= ~ISR_RXRDY(channel); in write_cr()
241 blk->isr &= ~ISR_TXRDY(channel); in write_cr()
249 blk->isr &= ~(ISR_BREAKA | ISR_BREAKB); in write_cr()
271 uint8_t old_isr = blk->isr; in io_read()
295 blk->isr &= ~ISR_RXRDY(channel); in io_read()
[all …]
H A Dmcf_uart.c26 uint8_t isr; member
71 s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT); in OBJECT_DECLARE_SIMPLE_TYPE()
73 s->isr |= MCF_UART_TxINT; in OBJECT_DECLARE_SIMPLE_TYPE()
76 s->isr |= MCF_UART_RxINT; in OBJECT_DECLARE_SIMPLE_TYPE()
78 qemu_set_irq(s->irq, (s->isr & s->imr) != 0); in OBJECT_DECLARE_SIMPLE_TYPE()
113 return s->isr; in mcf_uart_read()
161 s->isr &= ~MCF_UART_DBINT; in mcf_do_command()
243 s->isr = 0; in mcf_uart_reset()
268 s->isr |= MCF_UART_DBINT; in mcf_uart_event()
/openbmc/linux/arch/ia64/kernel/
H A Dtraps.c8 * 05/12/00 grao <goutham.rao@intel.com> : added isr in siginfo for SIGFPE
233 fp_emulate (int fp_fault, void *bundle, long *ipsr, long *fpsr, long *isr, long *pr, long *ifs, in fp_emulate() argument
265 (unsigned long *) isr, (unsigned long *) pr, in fp_emulate()
284 handle_fpu_swa (int fp_fault, struct pt_regs *regs, unsigned long isr) in handle_fpu_swa() argument
322 "%s(%d): floating-point assist fault at ip %016lx, isr %016lx\n", in handle_fpu_swa()
323 current->comm, task_pid_nr(current), regs->cr_iip + ia64_psr(regs)->ri, isr); in handle_fpu_swa()
328 exception = fp_emulate(fp_fault, bundle, &regs->cr_ipsr, &regs->ar_fpsr, &isr, &regs->pr, in handle_fpu_swa()
345 if (isr & 0x11) { in handle_fpu_swa()
347 } else if (isr & 0x22) { in handle_fpu_swa()
351 } else if (isr & 0x44) { in handle_fpu_swa()
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dast2600_i2c.c22 u32 isr; member
117 u32 cmd, isr; in ast2600_i2c_read_data() local
133 ret = readl_poll_timeout(&priv->regs->isr, isr, in ast2600_i2c_read_data()
134 isr & AST2600_I2CM_PKT_DONE, in ast2600_i2c_read_data()
142 writel(AST2600_I2CM_PKT_DONE, &priv->regs->isr); in ast2600_i2c_read_data()
144 if (isr & AST2600_I2CM_TX_NAK) in ast2600_i2c_read_data()
155 u32 cmd, isr; in ast2600_i2c_write_data() local
161 ret = readl_poll_timeout(&priv->regs->isr, isr, in ast2600_i2c_write_data()
162 isr & AST2600_I2CM_PKT_DONE, in ast2600_i2c_write_data()
166 if (isr & AST2600_I2CM_TX_NAK) in ast2600_i2c_write_data()
[all …]
/openbmc/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc-compat.c34 omap_dispc_isr_t isr; member
129 if (isr_data->isr == NULL) in _omap_dispc_set_irqs()
138 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) in omap_dispc_register_isr() argument
145 if (isr == NULL) in omap_dispc_register_isr()
153 if (isr_data->isr == isr && isr_data->arg == arg && in omap_dispc_register_isr()
166 if (isr_data->isr != NULL) in omap_dispc_register_isr()
169 isr_data->isr = isr; in omap_dispc_register_isr()
192 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) in omap_dispc_unregister_isr() argument
203 if (isr_data->isr != isr || isr_data->arg != arg || in omap_dispc_unregister_isr()
207 /* found the correct isr */ in omap_dispc_unregister_isr()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-pxa.c138 u32 isr; member
160 .isr = 0x18,
169 .isr = 0x0c,
178 .isr = 0x04,
187 .isr = 0x18,
198 .isr = 0x0c,
323 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); in decode_ISR()
355 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, in i2c_pxa_show_state()
370 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n", in i2c_pxa_scream_blue_murder()
427 u32 isr; in i2c_pxa_wait_bus_not_busy() local
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-stm32.c103 u16 isr; member
155 unsigned int isr = readl_relaxed(rtc->base + regs->isr); in stm32_rtc_enter_init_mode() local
157 if (!(isr & STM32_RTC_ISR_INITF)) { in stm32_rtc_enter_init_mode()
158 isr |= STM32_RTC_ISR_INIT; in stm32_rtc_enter_init_mode()
159 writel_relaxed(isr, rtc->base + regs->isr); in stm32_rtc_enter_init_mode()
167 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr, in stm32_rtc_enter_init_mode()
168 (isr & STM32_RTC_ISR_INITF), in stm32_rtc_enter_init_mode()
178 unsigned int isr = readl_relaxed(rtc->base + regs->isr); in stm32_rtc_exit_init_mode() local
180 isr &= ~STM32_RTC_ISR_INIT; in stm32_rtc_exit_init_mode()
181 writel_relaxed(isr, rtc->base + regs->isr); in stm32_rtc_exit_init_mode()
[all …]
/openbmc/linux/arch/mips/loongson2ef/lemote-2f/
H A Dirq.c28 * get the irq via the IRR directly, we access the ISR instead.
32 int irq, isr; in mach_i8259_irq() local
38 isr = inb(PIC_MASTER_CMD) & in mach_i8259_irq()
40 if (!isr) in mach_i8259_irq()
41 isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8; in mach_i8259_irq()
42 irq = ffs(isr) - 1; in mach_i8259_irq()
47 * Read the interrupt status register (ISR). If the most in mach_i8259_irq()
51 outb(0x0B, PIC_MASTER_ISR); /* ISR register */ in mach_i8259_irq()
/openbmc/qemu/hw/gpio/
H A Dimx_gpio.c61 return "ISR"; in imx_gpio_reg_name()
72 qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0); in imx_gpio_update_int()
73 qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0); in imx_gpio_update_int()
75 qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0); in imx_gpio_update_int()
91 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
98 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
104 s->isr = deposit32(s->isr, line, 1, 1); in imx_gpio_set_int_line()
184 reg_value = s->isr; in imx_gpio_read()
244 s->isr &= ~value; in imx_gpio_write()
286 VMSTATE_UINT32(isr, IMXGPIOState),
[all …]
/openbmc/linux/arch/ia64/mm/
H A Dfault.c66 ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *regs) in ia64_do_page_fault() argument
75 mask = ((((isr >> IA64_ISR_X_BIT) & 1UL) << VM_EXEC_BIT) in ia64_do_page_fault()
76 | (((isr >> IA64_ISR_W_BIT) & 1UL) << VM_WRITE_BIT)); in ia64_do_page_fault()
128 if (((isr >> IA64_ISR_R_BIT) & 1UL) && (!(vma->vm_flags & (VM_READ | VM_WRITE)))) in ia64_do_page_fault()
185 if ((isr & IA64_ISR_SP) in ia64_do_page_fault()
186 || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH)) in ia64_do_page_fault()
198 0, __ISR_VALID, isr); in ia64_do_page_fault()
203 if ((isr & IA64_ISR_SP) in ia64_do_page_fault()
204 || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH)) in ia64_do_page_fault()
239 if (die("Oops", regs, isr)) in ia64_do_page_fault()
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c35 u32 isr = 0; in ar9002_hw_get_isr() local
46 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
55 if (!isr && !sync_cause) in ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
62 if (isr) { in ar9002_hw_get_isr()
63 if (isr & AR_ISR_BCNMISC) { in ar9002_hw_get_isr()
83 isr &= ~AR_ISR_BCNMISC; in ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
90 if (isr == 0xffffffff) { in ar9002_hw_get_isr()
95 *masked = isr & ATH9K_INT_COMMON; in ar9002_hw_get_isr()
[all …]
H A Dar9003_mac.c186 u32 isr = 0; in ar9003_hw_get_isr() local
201 isr = REG_READ(ah, AR_ISR); in ar9003_hw_get_isr()
209 if (!isr && !sync_cause && !async_cause) in ar9003_hw_get_isr()
212 if (isr) { in ar9003_hw_get_isr()
213 if (isr & AR_ISR_BCNMISC) { in ar9003_hw_get_isr()
236 isr &= ~AR_ISR_BCNMISC; in ar9003_hw_get_isr()
241 isr = REG_READ(ah, AR_ISR_RAC); in ar9003_hw_get_isr()
243 if (isr == 0xffffffff) { in ar9003_hw_get_isr()
248 *masked = isr & ATH9K_INT_COMMON; in ar9003_hw_get_isr()
251 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) in ar9003_hw_get_isr()
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dtimbuart.c35 static void timbuart_mctrl_check(struct uart_port *port, u32 isr, u32 *ier);
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty() local
66 return (isr & TXBE) ? TIOCSER_TEMT : 0; in timbuart_tx_empty()
116 static void timbuart_handle_tx_port(struct uart_port *port, u32 isr, u32 *ier) in timbuart_handle_tx_port() argument
128 if (isr & TXFLAGS) { in timbuart_handle_tx_port()
150 static void timbuart_handle_rx_port(struct uart_port *port, u32 isr, u32 *ier) in timbuart_handle_rx_port() argument
152 if (isr & RXFLAGS) { in timbuart_handle_rx_port()
154 if (isr & RXBF) { in timbuart_handle_rx_port()
159 } else if (isr & (RXDP)) in timbuart_handle_rx_port()
175 u32 isr, ier = 0; in timbuart_tasklet() local
[all …]
/openbmc/linux/arch/arc/kernel/
H A Dintc-compact.c136 * which maybe in hard ISR itself
140 * -If called from hard-ISR, it must not invert interrupt priorities
142 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
144 * -If called from soft-ISR, it must re-enable all interrupts
145 * soft ISR are low priority jobs which can be very slow, thus all IRQs
147 * Now hardware context wise we may still be in L2 ISR (not done rtie)
150 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
/openbmc/linux/drivers/media/common/saa7146/
H A Dsaa7146_core.c272 u32 isr; in interrupt_hw() local
276 ack_isr = isr = saa7146_read(dev, ISR); in interrupt_hw()
279 if ( 0 == isr ) { in interrupt_hw()
285 if (dev->ext->irq_mask & isr) { in interrupt_hw()
287 dev->ext->irq_func(dev, &isr); in interrupt_hw()
288 isr &= ~dev->ext->irq_mask; in interrupt_hw()
291 if (0 != (isr & (MASK_27))) { in interrupt_hw()
292 DEB_INT("irq: RPS0 (0x%08x)\n", isr); in interrupt_hw()
294 dev->vv_callback(dev,isr); in interrupt_hw()
295 isr &= ~MASK_27; in interrupt_hw()
[all …]
/openbmc/u-boot/arch/microblaze/cpu/
H A Dinterrupts.c57 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in enable_one_interrupt()
72 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in disable_one_interrupt()
110 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in intc_init()
166 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in interrupt_handler()
180 debug("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr, in interrupt_handler()
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c39 REG32(ISR, 0x1C)
40 FIELD(ISR, REACK, 22, 1)
41 FIELD(ISR, TEACK, 21, 1)
42 FIELD(ISR, TXE, 7, 1)
43 FIELD(ISR, RXNE, 5, 1)
44 FIELD(ISR, ORE, 3, 1)
307 uint32_t isr; in test_ack() local
318 /* Test ISR ACK for transmitter and receiver disabled */ in test_ack()
319 isr = qtest_readl(qts, (USART1_BASE_ADDR + A_ISR)); in test_ack()
320 g_assert_false(isr & R_ISR_TEACK_MASK); in test_ack()
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A Daspeed_usbtty.c448 u32 isr = ast_udc_read(AST_VHUB_ISR); in udc_irq() local
452 if (!isr) in udc_irq()
455 if (isr & ISR_BUS_RESET) { in udc_irq()
461 if (isr & ISR_BUS_SUSPEND) { in udc_irq()
467 if (isr & ISR_SUSPEND_RESUME) { in udc_irq()
473 if (isr & ISR_HUB_EP0_IN_ACK_STALL) { in udc_irq()
479 if (isr & ISR_HUB_EP0_OUT_ACK_STALL) { in udc_irq()
485 if (isr & ISR_HUB_EP0_OUT_NAK) { in udc_irq()
490 if (isr & ISR_HUB_EP0_IN_DATA_NAK) { in udc_irq()
495 if (isr & ISR_HUB_EP0_SETUP) { in udc_irq()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_aux.c385 u32 isr; in dp_aux_isr() local
395 isr = dp_catalog_aux_get_irq(aux->catalog); in dp_aux_isr()
398 if (!isr) in dp_aux_isr()
402 DRM_ERROR("Unexpected DP AUX IRQ %#010x when not busy\n", isr); in dp_aux_isr()
412 if (hweight32(isr & ~DP_INTR_AUX_XFER_DONE) > 1) in dp_aux_isr()
413 DRM_WARN("Some DP AUX interrupts unhandled: %#010x\n", isr); in dp_aux_isr()
415 if (isr & DP_INTR_AUX_ERROR) { in dp_aux_isr()
418 } else if (isr & DP_INTR_NACK_DEFER) { in dp_aux_isr()
420 } else if (isr & DP_INTR_WRONG_ADDR) { in dp_aux_isr()
422 } else if (isr & DP_INTR_TIMEOUT) { in dp_aux_isr()
[all …]
/openbmc/linux/drivers/mfd/
H A Dtwl4030-irq.c62 u8 bits; /* valid in isr/imr */
63 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */
288 pr_warn("twl4030: I2C error %d reading PIH ISR\n", ret); in handle_twl4030_pih()
388 status, sih->name, "ISR"); in twl4030_init_sih_modules()
566 } isr; in sih_read_isr() local
570 isr.word = 0; in sih_read_isr()
571 status = twl_i2c_read(sih->module, isr.bytes, in sih_read_isr()
574 return (status < 0) ? status : le32_to_cpu(isr.word); in sih_read_isr()
585 int isr; in handle_twl4030_sih() local
587 /* reading ISR acks the IRQs, using clear-on-read mode */ in handle_twl4030_sih()
[all …]

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