| /openbmc/linux/arch/sparc/kernel/ |
| H A D | iommu.c | 2 /* iommu.c: Generic sparc64 IOMMU support.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
49 /* Must be invoked under the IOMMU lock. */
52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
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| H A D | iommu-common.c | 3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
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| /openbmc/linux/drivers/iommu/ |
| H A D | sun50i-iommu.c | 14 #include <linux/iommu.h>
99 struct iommu_device iommu; member
101 /* Lock to modify the IOMMU registers */
124 struct sun50i_iommu *iommu; member
137 static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) in iommu_read() argument
139 return readl(iommu->base + offset); in iommu_read()
142 static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) in iommu_write() argument
144 writel(value, iommu->base + offset); in iommu_write()
148 * The Allwinner H6 IOMMU uses a 2-level page table.
157 * The IOMMU supports a single DT, pointed by the IOMMU_TTB_REG
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| H A D | msm_iommu.c | 18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
73 if (iommu->clk) in __disable_clocks()
74 clk_disable(iommu->clk); in __disable_clocks()
75 clk_disable(iommu->pclk); in __disable_clocks()
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| H A D | rockchip-iommu.c | 3 * IOMMU API for Rockchip
17 #include <linux/iommu.h>
92 /* list of clocks required by IOMMU */
113 struct iommu_device iommu; member
115 struct iommu_domain *domain; /* domain to which iommu is attached */
120 struct device_link *link; /* runtime PM link from IOMMU to master */
121 struct rk_iommu *iommu; member
142 * The Rockchip rk3288 iommu uses a 2-level page table.
151 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
304 * rk3288 iova (IOMMU Virtual Address) format
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| H A D | iommu-sysfs.c | 3 * IOMMU sysfs class support
10 #include <linux/iommu.h>
16 * As devices are added to the IOMMU, we'll add links to the group.
38 .name = "iommu",
50 * Init the struct device for the IOMMU. IOMMU specific attributes can
52 * IOMMU type.
54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc(sizeof(*iommu->dev), GFP_KERNEL); in iommu_device_sysfs_add()
63 if (!iommu->dev) in iommu_device_sysfs_add()
66 device_initialize(iommu->dev); in iommu_device_sysfs_add()
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| H A D | Kconfig | 11 bool "IOMMU Hardware Support"
22 menu "Generic IOMMU Pagetable Support"
56 for 64KB pages/16MB supersections if indicated by the IOMMU driver.
82 bool "Export IOMMU internals in DebugFS"
85 Allows exposure of IOMMU device internals. This option enables
86 the use of debugfs by IOMMU drivers as required. Devices can,
87 at initialization time, cause the IOMMU code to create a top-level
88 debug/iommu directory, and then populate a subdirectory with
92 prompt "IOMMU default domain type"
97 Choose the type of IOMMU domain used to manage DMA API usage by
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-iommu.txt | 2 relationship between PCI(e) devices and IOMMU(s).
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
42 the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
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| /openbmc/linux/drivers/iommu/amd/ |
| H A D | init.c | 20 #include <linux/amd-iommu.h>
26 #include <asm/iommu.h>
99 * structure describing one IOMMU in the ACPI table. Typically followed by one
119 * A device entry describing which devices a specific IOMMU translates and
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
199 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
239 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
241 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
244 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
246 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
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| H A D | iommu.c | 21 #include <linux/iommu-helper.h>
23 #include <linux/amd-iommu.h>
37 #include <asm/iommu.h>
42 #include "../dma-iommu.h"
73 * general struct to manage commands send to an IOMMU
122 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu) in get_dev_table() argument
125 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in get_dev_table()
151 /* Writes the specific IOMMU for a device into the PCI segment rlookup table */
152 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid) in amd_iommu_set_rlookup_table() argument
154 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in amd_iommu_set_rlookup_table()
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| /openbmc/linux/drivers/iommu/intel/ |
| H A D | cap_audit.c | 3 * cap_audit.c - audit iommu capabilities for boot time and hot plug
13 #include "iommu.h"
74 static int cap_audit_hotplug(struct intel_iommu *iommu, enum cap_audit_type type) in cap_audit_hotplug() argument
81 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pi_support, CAP_PI_MASK); in cap_audit_hotplug()
82 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, eim_support, ECAP_EIM_MASK); in cap_audit_hotplug()
86 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl5lp_support, CAP_FL5LP_MASK); in cap_audit_hotplug()
87 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, fl1gp_support, CAP_FL1GP_MASK); in cap_audit_hotplug()
88 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, read_drain, CAP_RD_MASK); in cap_audit_hotplug()
89 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, write_drain, CAP_WD_MASK); in cap_audit_hotplug()
90 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, cap, pgsel_inv, CAP_PSI_MASK); in cap_audit_hotplug()
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| H A D | irq_remapping.c | 23 #include "iommu.h"
33 struct intel_iommu *iommu; member
40 struct intel_iommu *iommu; member
47 struct intel_iommu *iommu; member
74 * ->iommu->register_lock
83 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
87 static bool ir_pre_enabled(struct intel_iommu *iommu) in ir_pre_enabled() argument
89 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
92 static void clear_ir_pre_enabled(struct intel_iommu *iommu) in clear_ir_pre_enabled() argument
94 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; in clear_ir_pre_enabled()
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| H A D | svm.c | 22 #include "iommu.h"
25 #include "../iommu-sva.h"
64 int intel_svm_enable_prq(struct intel_iommu *iommu) in intel_svm_enable_prq() argument
70 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, PRQ_ORDER); in intel_svm_enable_prq()
72 pr_warn("IOMMU: %s: Failed to allocate page request queue\n", in intel_svm_enable_prq()
73 iommu->name); in intel_svm_enable_prq()
76 iommu->prq = page_address(pages); in intel_svm_enable_prq()
78 irq = dmar_alloc_hwirq(IOMMU_IRQ_ID_OFFSET_PRQ + iommu->seq_id, iommu->node, iommu); in intel_svm_enable_prq()
80 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n", in intel_svm_enable_prq()
81 iommu->name); in intel_svm_enable_prq()
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| H A D | iommu.c | 27 #include "iommu.h"
28 #include "../dma-iommu.h"
30 #include "../iommu-sva.h"
223 static inline bool context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn) in context_copied() argument
225 if (!iommu->copied_tables) in context_copied()
228 return test_bit(((long)bus << 8) | devfn, iommu->copied_tables); in context_copied()
232 set_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn) in set_context_copied() argument
234 set_bit(((long)bus << 8) | devfn, iommu->copied_tables); in set_context_copied()
238 clear_context_copied(struct intel_iommu *iommu, u8 bus, u8 devfn) in clear_context_copied() argument
240 clear_bit(((long)bus << 8) | devfn, iommu->copied_tables); in clear_context_copied()
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| H A D | dmar.c | 28 #include <linux/iommu.h>
33 #include "iommu.h"
67 static void free_iommu(struct intel_iommu *iommu);
461 if (dmaru->iommu) in dmar_free_drhd()
462 free_iommu(dmaru->iommu); in dmar_free_drhd()
501 drhd->iommu->node = node; in dmar_parse_one_rhsa()
766 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
939 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
952 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
954 iounmap(iommu->reg); in unmap_iommu()
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| H A D | pasid.c | 15 #include <linux/iommu.h>
21 #include "iommu.h"
25 * Intel IOMMU system wide PASID name space:
29 int vcmd_alloc_pasid(struct intel_iommu *iommu, u32 *pasid) in vcmd_alloc_pasid() argument
36 raw_spin_lock_irqsave(&iommu->register_lock, flags); in vcmd_alloc_pasid()
37 dmar_writeq(iommu->reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC); in vcmd_alloc_pasid()
38 IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq, in vcmd_alloc_pasid()
40 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in vcmd_alloc_pasid()
48 pr_info("IOMMU: %s: No PASID available\n", iommu->name); in vcmd_alloc_pasid()
53 pr_warn("IOMMU: %s: Unexpected error code %d\n", in vcmd_alloc_pasid()
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| H A D | debugfs.c | 17 #include "iommu.h"
117 struct intel_iommu *iommu; in iommu_regset_show() local
123 for_each_active_iommu(iommu, drhd) { in iommu_regset_show()
125 seq_puts(m, "IOMMU: Invalid base address\n"); in iommu_regset_show()
130 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in iommu_regset_show()
131 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
137 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_regset_show()
139 value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); in iommu_regset_show()
145 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); in iommu_regset_show()
150 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_regset_show()
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| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
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| H A D | qcom,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
14 a similar looking IOMMU, but without access to the global register space
23 - qcom,msm8916-iommu
24 - qcom,msm8953-iommu
25 - const: qcom,msm-iommu-v1
28 - qcom,msm8976-iommu
29 - const: qcom,msm-iommu-v2
33 - description: Clock required for IOMMU register group access
49 qcom,iommu-secure-id:
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| H A D | ti,omap-iommu.txt | 1 OMAP2+ IOMMU
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
16 Documentation/devicetree/bindings/iommu/iommu.txt
21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
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| H A D | msm,iommu-v0.txt | 1 * QCOM IOMMU
3 The MSM IOMMU is an implementation compatible with the ARM VMSA short
5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
27 required for iommu's register accesses.
29 required by iommu for bus accesses.
31 Each bus master connected to an IOMMU must reference the IOMMU in its device
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| /openbmc/linux/drivers/vfio/ |
| H A D | vfio_iommu_type1.c | 3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
28 #include <linux/iommu.h>
44 #define DRIVER_DESC "Type1 IOMMU driver for VFIO"
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| /openbmc/linux/arch/powerpc/platforms/cell/ |
| H A D | iommu.c | 3 * IOMMU implementation for Cell Broadband Processor Architecture
24 #include <asm/iommu.h>
95 /* IOMMU sizing */
104 struct cbe_iommu *iommu; member
131 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, in invalidate_tce_cache() argument
138 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; in invalidate_tce_cache()
195 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_build_cell()
218 __pa(window->iommu->pad_page) | in tce_free_cell()
229 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_free_cell()
235 struct cbe_iommu *iommu = data; in ioc_interrupt() local
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| /openbmc/qemu/docs/ |
| H A D | bypass-iommu.txt | 1 BYPASS IOMMU PROPERTY
8 is not flexible. We introduce this bypass iommu property to support
10 passthrough devices with no-iommu mode and devices go through vIOMMU in
15 virtual iommu. The bypass_iommu property is valid only when there is a
16 virtual iommu in the system, it is implemented to allow some devices to
22 The bypass iommu feature support PXB host bridge and default main host
26 on AArch64. Other machine types do not support bypass iommu for default
29 1. The following is the bypass iommu options:
33 qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
34 (3) X86 default root bus bypass iommu:
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| /openbmc/linux/arch/sparc/mm/ |
| H A D | iommu.c | 3 * iommu.c: IOMMU specific routines for memory management.
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
75 if (!iommu->regs) { in sbus_iommu_init()
76 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
80 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
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