Lines Matching full:iommu
28 #include <linux/iommu.h>
33 #include "iommu.h"
67 static void free_iommu(struct intel_iommu *iommu);
461 if (dmaru->iommu) in dmar_free_drhd()
462 free_iommu(dmaru->iommu); in dmar_free_drhd()
501 drhd->iommu->node = node; in dmar_parse_one_rhsa()
766 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
939 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
952 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
954 iounmap(iommu->reg); in unmap_iommu()
955 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
959 * map_iommu: map the iommu's registers
960 * @iommu: the iommu to map
963 * Memory map the iommu's registers. Start w/ a single page, and
966 static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd) in map_iommu() argument
971 iommu->reg_phys = phys_addr; in map_iommu()
972 iommu->reg_size = drhd->reg_size; in map_iommu()
974 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { in map_iommu()
980 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
981 if (!iommu->reg) { in map_iommu()
987 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
988 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
990 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { in map_iommu()
997 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), in map_iommu()
998 cap_max_fault_reg_offset(iommu->cap)); in map_iommu()
1000 if (map_size > iommu->reg_size) { in map_iommu()
1001 iounmap(iommu->reg); in map_iommu()
1002 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1003 iommu->reg_size = map_size; in map_iommu()
1004 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, in map_iommu()
1005 iommu->name)) { in map_iommu()
1010 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
1011 if (!iommu->reg) { in map_iommu()
1018 if (cap_ecmds(iommu->cap)) { in map_iommu()
1022 iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG + in map_iommu()
1031 iounmap(iommu->reg); in map_iommu()
1033 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1040 struct intel_iommu *iommu; in alloc_iommu() local
1051 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); in alloc_iommu()
1052 if (!iommu) in alloc_iommu()
1055 iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0, in alloc_iommu()
1057 if (iommu->seq_id < 0) { in alloc_iommu()
1059 err = iommu->seq_id; in alloc_iommu()
1062 sprintf(iommu->name, "dmar%d", iommu->seq_id); in alloc_iommu()
1064 err = map_iommu(iommu, drhd); in alloc_iommu()
1066 pr_err("Failed to map %s\n", iommu->name); in alloc_iommu()
1071 if (!cap_sagaw(iommu->cap) && in alloc_iommu()
1072 (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) { in alloc_iommu()
1074 iommu->name); in alloc_iommu()
1079 agaw = iommu_calculate_agaw(iommu); in alloc_iommu()
1081 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", in alloc_iommu()
1082 iommu->seq_id); in alloc_iommu()
1087 msagaw = iommu_calculate_max_sagaw(iommu); in alloc_iommu()
1089 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", in alloc_iommu()
1090 iommu->seq_id); in alloc_iommu()
1095 iommu->agaw = agaw; in alloc_iommu()
1096 iommu->msagaw = msagaw; in alloc_iommu()
1097 iommu->segment = drhd->segment; in alloc_iommu()
1099 iommu->node = NUMA_NO_NODE; in alloc_iommu()
1101 ver = readl(iommu->reg + DMAR_VER_REG); in alloc_iommu()
1103 iommu->name, in alloc_iommu()
1106 (unsigned long long)iommu->cap, in alloc_iommu()
1107 (unsigned long long)iommu->ecap); in alloc_iommu()
1110 sts = readl(iommu->reg + DMAR_GSTS_REG); in alloc_iommu()
1112 iommu->gcmd |= DMA_GCMD_IRE; in alloc_iommu()
1114 iommu->gcmd |= DMA_GCMD_TE; in alloc_iommu()
1116 iommu->gcmd |= DMA_GCMD_QIE; in alloc_iommu()
1118 if (alloc_iommu_pmu(iommu)) in alloc_iommu()
1119 pr_debug("Cannot alloc PMU for iommu (seq_id = %d)\n", iommu->seq_id); in alloc_iommu()
1121 raw_spin_lock_init(&iommu->register_lock); in alloc_iommu()
1127 if (pasid_supported(iommu)) in alloc_iommu()
1128 iommu->iommu.max_pasids = 2UL << ecap_pss(iommu->ecap); in alloc_iommu()
1136 err = iommu_device_sysfs_add(&iommu->iommu, NULL, in alloc_iommu()
1138 "%s", iommu->name); in alloc_iommu()
1142 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); in alloc_iommu()
1146 iommu_pmu_register(iommu); in alloc_iommu()
1149 drhd->iommu = iommu; in alloc_iommu()
1150 iommu->drhd = drhd; in alloc_iommu()
1155 iommu_device_sysfs_remove(&iommu->iommu); in alloc_iommu()
1157 free_iommu_pmu(iommu); in alloc_iommu()
1158 unmap_iommu(iommu); in alloc_iommu()
1160 ida_free(&dmar_seq_ids, iommu->seq_id); in alloc_iommu()
1162 kfree(iommu); in alloc_iommu()
1166 static void free_iommu(struct intel_iommu *iommu) in free_iommu() argument
1168 if (intel_iommu_enabled && !iommu->drhd->ignored) { in free_iommu()
1169 iommu_pmu_unregister(iommu); in free_iommu()
1170 iommu_device_unregister(&iommu->iommu); in free_iommu()
1171 iommu_device_sysfs_remove(&iommu->iommu); in free_iommu()
1174 free_iommu_pmu(iommu); in free_iommu()
1176 if (iommu->irq) { in free_iommu()
1177 if (iommu->pr_irq) { in free_iommu()
1178 free_irq(iommu->pr_irq, iommu); in free_iommu()
1179 dmar_free_hwirq(iommu->pr_irq); in free_iommu()
1180 iommu->pr_irq = 0; in free_iommu()
1182 free_irq(iommu->irq, iommu); in free_iommu()
1183 dmar_free_hwirq(iommu->irq); in free_iommu()
1184 iommu->irq = 0; in free_iommu()
1187 if (iommu->qi) { in free_iommu()
1188 free_page((unsigned long)iommu->qi->desc); in free_iommu()
1189 kfree(iommu->qi->desc_status); in free_iommu()
1190 kfree(iommu->qi); in free_iommu()
1193 if (iommu->reg) in free_iommu()
1194 unmap_iommu(iommu); in free_iommu()
1196 ida_free(&dmar_seq_ids, iommu->seq_id); in free_iommu()
1197 kfree(iommu); in free_iommu()
1237 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault) in qi_dump_fault() argument
1239 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG); in qi_dump_fault()
1240 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); in qi_dump_fault()
1241 struct qi_desc *desc = iommu->qi->desc + head; in qi_dump_fault()
1258 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH; in qi_dump_fault()
1259 head <<= qi_shift(iommu); in qi_dump_fault()
1260 desc = iommu->qi->desc + head; in qi_dump_fault()
1268 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index) in qi_check_fault() argument
1272 struct q_inval *qi = iommu->qi; in qi_check_fault()
1273 int shift = qi_shift(iommu); in qi_check_fault()
1278 fault = readl(iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1280 qi_dump_fault(iommu, fault); in qi_check_fault()
1288 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1299 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1310 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1313 tail = readl(iommu->reg + DMAR_IQT_REG); in qi_check_fault()
1316 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1330 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1344 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, in qi_submit_sync() argument
1347 struct q_inval *qi = iommu->qi; in qi_submit_sync()
1364 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB)) in qi_submit_sync()
1368 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB)) in qi_submit_sync()
1372 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC)) in qi_submit_sync()
1392 shift = qi_shift(iommu); in qi_submit_sync()
1398 trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1, in qi_submit_sync()
1421 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); in qi_submit_sync()
1431 rc = qi_check_fault(iommu, index, wait_index); in qi_submit_sync()
1458 dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB, in qi_submit_sync()
1462 dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB, in qi_submit_sync()
1466 dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC, in qi_submit_sync()
1475 void qi_global_iec(struct intel_iommu *iommu) in qi_global_iec() argument
1485 qi_submit_sync(iommu, &desc, 1, 0); in qi_global_iec()
1488 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, in qi_flush_context() argument
1499 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_context()
1502 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, in qi_flush_iotlb() argument
1510 if (cap_write_drain(iommu->cap)) in qi_flush_iotlb()
1513 if (cap_read_drain(iommu->cap)) in qi_flush_iotlb()
1523 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_iotlb()
1526 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, in qi_flush_dev_iotlb() argument
1537 if (!(iommu->gcmd & DMA_GCMD_TE)) in qi_flush_dev_iotlb()
1554 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_dev_iotlb()
1558 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, in qi_flush_piotlb() argument
1595 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_piotlb()
1599 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, in qi_flush_dev_iotlb_pasid() argument
1611 if (!(iommu->gcmd & DMA_GCMD_TE)) in qi_flush_dev_iotlb_pasid()
1648 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_dev_iotlb_pasid()
1651 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, in qi_flush_pasid_cache() argument
1658 qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_pasid_cache()
1664 void dmar_disable_qi(struct intel_iommu *iommu) in dmar_disable_qi() argument
1670 if (!ecap_qis(iommu->ecap)) in dmar_disable_qi()
1673 raw_spin_lock_irqsave(&iommu->register_lock, flags); in dmar_disable_qi()
1675 sts = readl(iommu->reg + DMAR_GSTS_REG); in dmar_disable_qi()
1682 while ((readl(iommu->reg + DMAR_IQT_REG) != in dmar_disable_qi()
1683 readl(iommu->reg + DMAR_IQH_REG)) && in dmar_disable_qi()
1687 iommu->gcmd &= ~DMA_GCMD_QIE; in dmar_disable_qi()
1688 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in dmar_disable_qi()
1690 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, in dmar_disable_qi()
1693 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in dmar_disable_qi()
1699 static void __dmar_enable_qi(struct intel_iommu *iommu) in __dmar_enable_qi() argument
1703 struct q_inval *qi = iommu->qi; in __dmar_enable_qi()
1713 if (ecap_smts(iommu->ecap)) in __dmar_enable_qi()
1716 raw_spin_lock_irqsave(&iommu->register_lock, flags); in __dmar_enable_qi()
1719 writel(0, iommu->reg + DMAR_IQT_REG); in __dmar_enable_qi()
1721 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
1723 iommu->gcmd |= DMA_GCMD_QIE; in __dmar_enable_qi()
1724 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in __dmar_enable_qi()
1727 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); in __dmar_enable_qi()
1729 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in __dmar_enable_qi()
1737 int dmar_enable_qi(struct intel_iommu *iommu) in dmar_enable_qi() argument
1742 if (!ecap_qis(iommu->ecap)) in dmar_enable_qi()
1748 if (iommu->qi) in dmar_enable_qi()
1751 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); in dmar_enable_qi()
1752 if (!iommu->qi) in dmar_enable_qi()
1755 qi = iommu->qi; in dmar_enable_qi()
1761 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, in dmar_enable_qi()
1762 !!ecap_smts(iommu->ecap)); in dmar_enable_qi()
1765 iommu->qi = NULL; in dmar_enable_qi()
1775 iommu->qi = NULL; in dmar_enable_qi()
1781 __dmar_enable_qi(iommu); in dmar_enable_qi()
1786 /* iommu interrupt handling. Most stuff are MSI-like. */
1901 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) in dmar_msi_reg() argument
1903 if (iommu->irq == irq) in dmar_msi_reg()
1905 else if (iommu->pr_irq == irq) in dmar_msi_reg()
1907 else if (iommu->perf_irq == irq) in dmar_msi_reg()
1915 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); in dmar_msi_unmask() local
1916 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_unmask()
1920 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_unmask()
1921 writel(0, iommu->reg + reg); in dmar_msi_unmask()
1923 readl(iommu->reg + reg); in dmar_msi_unmask()
1924 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_unmask()
1929 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); in dmar_msi_mask() local
1930 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_mask()
1934 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_mask()
1935 writel(DMA_FECTL_IM, iommu->reg + reg); in dmar_msi_mask()
1937 readl(iommu->reg + reg); in dmar_msi_mask()
1938 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_mask()
1943 struct intel_iommu *iommu = irq_get_handler_data(irq); in dmar_msi_write() local
1944 int reg = dmar_msi_reg(iommu, irq); in dmar_msi_write()
1947 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_write()
1948 writel(msg->data, iommu->reg + reg + 4); in dmar_msi_write()
1949 writel(msg->address_lo, iommu->reg + reg + 8); in dmar_msi_write()
1950 writel(msg->address_hi, iommu->reg + reg + 12); in dmar_msi_write()
1951 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_write()
1956 struct intel_iommu *iommu = irq_get_handler_data(irq); in dmar_msi_read() local
1957 int reg = dmar_msi_reg(iommu, irq); in dmar_msi_read()
1960 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_read()
1961 msg->data = readl(iommu->reg + reg + 4); in dmar_msi_read()
1962 msg->address_lo = readl(iommu->reg + reg + 8); in dmar_msi_read()
1963 msg->address_hi = readl(iommu->reg + reg + 12); in dmar_msi_read()
1964 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_read()
1967 static int dmar_fault_do_one(struct intel_iommu *iommu, int type, in dmar_fault_do_one() argument
1998 dmar_fault_dump_ptes(iommu, source_id, addr, pasid); in dmar_fault_do_one()
2006 struct intel_iommu *iommu = dev_id; in dmar_fault() local
2014 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
2015 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in dmar_fault()
2024 reg = cap_fault_reg_offset(iommu->cap); in dmar_fault()
2037 data = readl(iommu->reg + reg + in dmar_fault()
2047 data = readl(iommu->reg + reg + in dmar_fault()
2052 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
2058 writel(DMA_FRCD_F, iommu->reg + reg + in dmar_fault()
2061 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2065 dmar_fault_do_one(iommu, type, fault_reason, in dmar_fault()
2070 if (fault_index >= cap_num_fault_regs(iommu->cap)) in dmar_fault()
2072 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
2076 iommu->reg + DMAR_FSTS_REG); in dmar_fault()
2079 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2083 int dmar_set_interrupt(struct intel_iommu *iommu) in dmar_set_interrupt() argument
2090 if (iommu->irq) in dmar_set_interrupt()
2093 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); in dmar_set_interrupt()
2095 iommu->irq = irq; in dmar_set_interrupt()
2101 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); in dmar_set_interrupt()
2110 struct intel_iommu *iommu; in enable_drhd_fault_handling() local
2115 for_each_iommu(iommu, drhd) { in enable_drhd_fault_handling()
2117 int ret = dmar_set_interrupt(iommu); in enable_drhd_fault_handling()
2128 dmar_fault(iommu->irq, iommu); in enable_drhd_fault_handling()
2129 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2130 writel(fault_status, iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2139 int dmar_reenable_qi(struct intel_iommu *iommu) in dmar_reenable_qi() argument
2141 if (!ecap_qis(iommu->ecap)) in dmar_reenable_qi()
2144 if (!iommu->qi) in dmar_reenable_qi()
2150 dmar_disable_qi(iommu); in dmar_reenable_qi()
2156 __dmar_enable_qi(iommu); in dmar_reenable_qi()