Lines Matching full:iommu
20 #include <linux/amd-iommu.h>
26 #include <asm/iommu.h>
99 * structure describing one IOMMU in the ACPI table. Typically followed by one
119 * A device entry describing which devices a specific IOMMU translates and
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
199 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
239 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
241 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
244 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
246 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
249 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
253 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
255 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
277 struct amd_iommu *iommu; in get_global_efr() local
279 for_each_iommu(iommu) { in get_global_efr()
280 u64 tmp = iommu->features; in get_global_efr()
281 u64 tmp2 = iommu->features2; in get_global_efr()
283 if (list_is_first(&iommu->list, &amd_iommu_list)) { in get_global_efr()
294 …"Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", in get_global_efr()
296 iommu->index, iommu->pci_seg->id, in get_global_efr()
297 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), in get_global_efr()
298 PCI_FUNC(iommu->devid)); in get_global_efr()
322 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
326 iommu->features = h->efr_reg; in early_iommu_features_init()
327 iommu->features2 = h->efr_reg2; in early_iommu_features_init()
335 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
339 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
340 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
344 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
346 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
347 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
348 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
351 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
355 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
356 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
360 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
362 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
363 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
368 * AMD IOMMU MMIO register space handling functions
370 * These functions are used to program the IOMMU device registers in
376 * This function set the exclusion range in the IOMMU. DMA accesses to the
379 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
381 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
382 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
385 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
389 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
393 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
397 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
399 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
409 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
416 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
420 /* Programs the physical address of the device table into the IOMMU hardware */
421 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
424 u32 dev_table_size = iommu->pci_seg->dev_table_size; in iommu_set_device_table()
425 void *dev_table = (void *)get_dev_table(iommu); in iommu_set_device_table()
427 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
431 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
435 /* Generic functions to enable/disable certain features of the IOMMU. */
436 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
440 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
442 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
445 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
449 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
451 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
454 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
458 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
461 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
465 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
467 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
470 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
472 if (!iommu->mmio_base) in iommu_disable()
476 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
479 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
480 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
482 /* Disable IOMMU GA_LOG */ in iommu_disable()
483 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
484 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
486 /* Disable IOMMU PPR logging */ in iommu_disable()
487 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); in iommu_disable()
488 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); in iommu_disable()
490 /* Disable IOMMU hardware itself */ in iommu_disable()
491 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
494 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable()
498 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
513 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
515 if (iommu->mmio_base) in iommu_unmap_mmio_space()
516 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
517 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
538 * The functions below belong to the first pass of AMD IOMMU ACPI table
562 * After reading the highest device id from the IOMMU PCI capability header
657 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
681 /* Allocate per PCI segment IOMMU rlookup table. */
747 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
748 * write commands to that buffer later and the IOMMU will execute them
751 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
753 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
756 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
763 static void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, in amd_iommu_restart_log() argument
769 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
773 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); in amd_iommu_restart_log()
775 iommu_feature_disable(iommu, cntrl_log); in amd_iommu_restart_log()
776 iommu_feature_disable(iommu, cntrl_intr); in amd_iommu_restart_log()
778 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
780 iommu_feature_enable(iommu, cntrl_intr); in amd_iommu_restart_log()
781 iommu_feature_enable(iommu, cntrl_log); in amd_iommu_restart_log()
785 * This function restarts event logging in case the IOMMU experienced
788 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) in amd_iommu_restart_event_logging() argument
790 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, in amd_iommu_restart_event_logging()
796 * This function restarts event logging in case the IOMMU experienced
799 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) in amd_iommu_restart_ga_log() argument
801 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, in amd_iommu_restart_ga_log()
807 * This function restarts ppr logging in case the IOMMU experienced
810 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu) in amd_iommu_restart_ppr_log() argument
812 amd_iommu_restart_log(iommu, "PPR", CONTROL_PPRINT_EN, in amd_iommu_restart_ppr_log()
818 * This function resets the command buffer if the IOMMU stopped fetching
821 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
823 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
825 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
826 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
827 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
828 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
830 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
837 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
841 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
843 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
846 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
849 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
855 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
857 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
860 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
862 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
865 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, in iommu_alloc_4k_pages() argument
881 /* allocates the memory where the IOMMU will log its events to */
882 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
884 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
887 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
890 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
894 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
896 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
898 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
902 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
903 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
905 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
911 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
913 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
916 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
918 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
921 /* allocates the memory where the IOMMU will log its events to */
922 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
924 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
927 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
930 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
934 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
937 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
939 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
941 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
945 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
946 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
948 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); in iommu_enable_ppr_log()
949 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); in iommu_enable_ppr_log()
952 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
954 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
957 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
960 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
961 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); in free_ga_log()
966 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
971 if (!iommu->ga_log) in iommu_ga_log_enable()
974 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
975 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
977 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
979 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
981 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
982 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
985 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
986 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
989 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
1001 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
1006 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
1008 if (!iommu->ga_log) in iommu_init_ga_log()
1011 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
1013 if (!iommu->ga_log_tail) in iommu_init_ga_log()
1018 free_ga_log(iommu); in iommu_init_ga_log()
1023 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
1025 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); in alloc_cwwb_sem()
1027 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
1030 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
1032 if (iommu->cmd_sem) in free_cwwb_sem()
1033 free_page((unsigned long)iommu->cmd_sem); in free_cwwb_sem()
1036 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
1045 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
1049 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
1051 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
1054 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
1067 static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) in set_dev_entry_bit() argument
1069 struct dev_table_entry *dev_table = get_dev_table(iommu); in set_dev_entry_bit()
1083 static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) in get_dev_entry_bit() argument
1085 struct dev_table_entry *dev_table = get_dev_table(iommu); in get_dev_entry_bit()
1090 static bool __copy_device_table(struct amd_iommu *iommu) in __copy_device_table() argument
1093 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in __copy_device_table()
1101 /* Each IOMMU use separate device table with the same size */ in __copy_device_table()
1102 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in __copy_device_table()
1103 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in __copy_device_table()
1108 pr_err("The device table size of IOMMU:%d is not expected!\n", in __copy_device_table()
1109 iommu->index); in __copy_device_table()
1182 struct amd_iommu *iommu; in copy_device_table() local
1195 for_each_iommu(iommu) { in copy_device_table()
1196 if (pci_seg->id != iommu->pci_seg->id) in copy_device_table()
1198 if (!__copy_device_table(iommu)) in copy_device_table()
1207 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) in amd_iommu_apply_erratum_63() argument
1211 sysmgt = get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | in amd_iommu_apply_erratum_63()
1212 (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); in amd_iommu_apply_erratum_63()
1215 set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); in amd_iommu_apply_erratum_63()
1222 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1226 set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS); in set_dev_entry_from_acpi()
1228 set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS); in set_dev_entry_from_acpi()
1230 set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); in set_dev_entry_from_acpi()
1232 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1); in set_dev_entry_from_acpi()
1234 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2); in set_dev_entry_from_acpi()
1236 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); in set_dev_entry_from_acpi()
1238 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); in set_dev_entry_from_acpi()
1240 amd_iommu_apply_erratum_63(iommu, devid); in set_dev_entry_from_acpi()
1242 amd_iommu_set_rlookup_table(iommu, devid); in set_dev_entry_from_acpi()
1353 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1356 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1365 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in init_iommu_from_acpi()
1379 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1405 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1417 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1447 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1448 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1480 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1508 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1511 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1547 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1613 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1695 static void __init free_sysfs(struct amd_iommu *iommu) in free_sysfs() argument
1697 if (iommu->iommu.dev) { in free_sysfs()
1698 iommu_device_unregister(&iommu->iommu); in free_sysfs()
1699 iommu_device_sysfs_remove(&iommu->iommu); in free_sysfs()
1703 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1705 free_sysfs(iommu); in free_iommu_one()
1706 free_cwwb_sem(iommu); in free_iommu_one()
1707 free_command_buffer(iommu); in free_iommu_one()
1708 free_event_buffer(iommu); in free_iommu_one()
1709 free_ppr_log(iommu); in free_iommu_one()
1710 free_ga_log(iommu); in free_iommu_one()
1711 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1716 struct amd_iommu *iommu, *next; in free_iommu_all() local
1718 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1719 list_del(&iommu->list); in free_iommu_all()
1720 free_iommu_one(iommu); in free_iommu_all()
1721 kfree(iommu); in free_iommu_all()
1726 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1731 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1740 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1741 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1747 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1749 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1750 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1753 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1757 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1762 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1772 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1778 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1780 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1784 * This function glues the initialization function for one IOMMU
1786 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1788 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, in init_iommu_one() argument
1796 iommu->pci_seg = pci_seg; in init_iommu_one()
1798 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1799 atomic64_set(&iommu->cmd_sem_val, 0); in init_iommu_one()
1801 /* Add IOMMU to internal data structures */ in init_iommu_one()
1802 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1803 iommu->index = amd_iommus_present++; in init_iommu_one()
1805 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1810 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1811 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1814 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1816 iommu->devid = h->devid; in init_iommu_one()
1817 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1818 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1826 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1828 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1842 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1844 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1860 early_iommu_features_init(iommu, h); in init_iommu_one()
1867 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1868 iommu->mmio_phys_end); in init_iommu_one()
1869 if (!iommu->mmio_base) in init_iommu_one()
1872 return init_iommu_from_acpi(iommu, h); in init_iommu_one()
1875 static int __init init_iommu_one_late(struct amd_iommu *iommu) in init_iommu_one_late() argument
1879 if (alloc_cwwb_sem(iommu)) in init_iommu_one_late()
1882 if (alloc_command_buffer(iommu)) in init_iommu_one_late()
1885 if (alloc_event_buffer(iommu)) in init_iommu_one_late()
1888 iommu->int_enabled = false; in init_iommu_one_late()
1890 init_translation_status(iommu); in init_iommu_one_late()
1891 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one_late()
1892 iommu_disable(iommu); in init_iommu_one_late()
1893 clear_translation_pre_enabled(iommu); in init_iommu_one_late()
1894 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one_late()
1895 iommu->index); in init_iommu_one_late()
1898 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one_late()
1901 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one_late()
1907 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one_late()
1910 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; in init_iommu_one_late()
1942 * Iterates over all IOMMU entries in the ACPI table, allocates the
1943 * IOMMU structure and initializes it with init_iommu_one()
1949 struct amd_iommu *iommu; in init_iommu_all() local
1968 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1969 if (iommu == NULL) in init_iommu_all()
1972 ret = init_iommu_one(iommu, h, table); in init_iommu_all()
1984 /* Phase 3 : Enabling IOMMU features */ in init_iommu_all()
1985 for_each_iommu(iommu) { in init_iommu_all()
1986 ret = init_iommu_one_late(iommu); in init_iommu_all()
1994 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1997 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1999 if (!iommu_feature(iommu, FEATURE_PC)) in init_iommu_perf_ctr()
2004 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
2006 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
2007 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
2008 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
2017 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
2018 return sysfs_emit(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
2026 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_features() local
2027 return sysfs_emit(buf, "%llx:%llx\n", iommu->features2, iommu->features); in amd_iommu_show_features()
2038 .name = "amd-iommu",
2049 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
2052 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
2056 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
2060 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
2061 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); in late_iommu_features_init()
2063 if (!iommu->features) { in late_iommu_features_init()
2064 iommu->features = features; in late_iommu_features_init()
2065 iommu->features2 = features2; in late_iommu_features_init()
2073 if (features != iommu->features || in late_iommu_features_init()
2074 features2 != iommu->features2) { in late_iommu_features_init()
2077 features, iommu->features, in late_iommu_features_init()
2078 features2, iommu->features2); in late_iommu_features_init()
2082 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
2084 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
2087 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2088 PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
2089 iommu->devid & 0xff); in iommu_init_pci()
2090 if (!iommu->dev) in iommu_init_pci()
2093 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
2094 iommu->dev->match_driver = false; in iommu_init_pci()
2096 /* ACPI _PRT won't have an IRQ for IOMMU */ in iommu_init_pci()
2097 iommu->dev->irq_managed = 1; in iommu_init_pci()
2099 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
2100 &iommu->cap); in iommu_init_pci()
2102 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
2105 late_iommu_features_init(iommu); in iommu_init_pci()
2107 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
2112 pasmax = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
2120 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
2129 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
2130 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
2131 iommu->is_iommu_v2 = true; in iommu_init_pci()
2135 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
2138 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { in iommu_init_pci()
2144 init_iommu_perf_ctr(iommu); in iommu_init_pci()
2147 if (!iommu_feature(iommu, FEATURE_GIOSUP) || in iommu_init_pci()
2148 !iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
2157 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
2160 iommu->root_pdev = in iommu_init_pci()
2161 pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2162 iommu->dev->bus->number, in iommu_init_pci()
2170 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
2171 &iommu->stored_addr_lo); in iommu_init_pci()
2172 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
2173 &iommu->stored_addr_hi); in iommu_init_pci()
2176 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
2180 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
2183 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
2186 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
2187 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
2189 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
2190 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
2194 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); in iommu_init_pci()
2196 return pci_enable_device(iommu->dev); in iommu_init_pci()
2205 struct amd_iommu *iommu; in print_iommu_info() local
2207 for_each_iommu(iommu) { in print_iommu_info()
2208 struct pci_dev *pdev = iommu->dev; in print_iommu_info()
2211 pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr); in print_iommu_info()
2213 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
2214 pr_info("Extended features (%#llx, %#llx):", iommu->features, iommu->features2); in print_iommu_info()
2217 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
2221 if (iommu->features & FEATURE_GAM_VAPIC) in print_iommu_info()
2224 if (iommu->features & FEATURE_SNP) in print_iommu_info()
2243 struct amd_iommu *iommu; in amd_iommu_init_pci() local
2247 for_each_iommu(iommu) { in amd_iommu_init_pci()
2248 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
2250 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", in amd_iommu_init_pci()
2251 iommu->index, ret); in amd_iommu_init_pci()
2255 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
2271 for_each_iommu(iommu) in amd_iommu_init_pci()
2272 iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
2289 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
2293 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
2297 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
2301 iommu); in iommu_setup_msi()
2304 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2373 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_unmask_irq() local
2383 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); in intcapxt_unmask_irq()
2388 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_mask_irq() local
2390 writeq(0, iommu->mmio_base + irqd->hwirq); in intcapxt_mask_irq()
2412 .name = "IOMMU-MSI",
2453 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, in __iommu_setup_intcapxt() argument
2459 int node = dev_to_node(&iommu->dev->dev); in __iommu_setup_intcapxt()
2467 info.data = iommu; in __iommu_setup_intcapxt()
2477 thread_fn, 0, devname, iommu); in __iommu_setup_intcapxt()
2487 static int iommu_setup_intcapxt(struct amd_iommu *iommu) in iommu_setup_intcapxt() argument
2491 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), in iommu_setup_intcapxt()
2492 "AMD-Vi%d-Evt", iommu->index); in iommu_setup_intcapxt()
2493 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, in iommu_setup_intcapxt()
2499 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), in iommu_setup_intcapxt()
2500 "AMD-Vi%d-PPR", iommu->index); in iommu_setup_intcapxt()
2501 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, in iommu_setup_intcapxt()
2508 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), in iommu_setup_intcapxt()
2509 "AMD-Vi%d-GA", iommu->index); in iommu_setup_intcapxt()
2510 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, in iommu_setup_intcapxt()
2518 static int iommu_init_irq(struct amd_iommu *iommu) in iommu_init_irq() argument
2522 if (iommu->int_enabled) in iommu_init_irq()
2526 ret = iommu_setup_intcapxt(iommu); in iommu_init_irq()
2527 else if (iommu->dev->msi_cap) in iommu_init_irq()
2528 ret = iommu_setup_msi(iommu); in iommu_init_irq()
2535 iommu->int_enabled = true; in iommu_init_irq()
2539 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_irq()
2541 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_irq()
2697 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2699 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2700 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2701 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2703 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2704 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2705 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2707 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2708 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2709 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2711 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2712 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2713 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2716 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2718 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2721 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2724 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2728 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2730 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2731 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2735 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2743 /* Enable the iommu */ in iommu_apply_resume_quirks()
2747 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2748 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2749 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2750 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2751 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2756 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2760 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2763 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2764 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2767 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2773 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2774 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2777 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2783 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) in iommu_disable_irtcachedis() argument
2785 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable_irtcachedis()
2788 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) in iommu_enable_irtcachedis() argument
2800 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); in iommu_enable_irtcachedis()
2801 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_enable_irtcachedis()
2804 iommu->irtcachedis_enabled = true; in iommu_enable_irtcachedis()
2805 pr_info("iommu%d (%#06x) : IRT cache is %s\n", in iommu_enable_irtcachedis()
2806 iommu->index, iommu->devid, in iommu_enable_irtcachedis()
2807 iommu->irtcachedis_enabled ? "disabled" : "enabled"); in iommu_enable_irtcachedis()
2810 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2812 iommu_disable(iommu); in early_enable_iommu()
2813 iommu_init_flags(iommu); in early_enable_iommu()
2814 iommu_set_device_table(iommu); in early_enable_iommu()
2815 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2816 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2817 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2818 iommu_enable_ga(iommu); in early_enable_iommu()
2819 iommu_enable_xt(iommu); in early_enable_iommu()
2820 iommu_enable_irtcachedis(iommu); in early_enable_iommu()
2821 iommu_enable(iommu); in early_enable_iommu()
2822 iommu_flush_all_caches(iommu); in early_enable_iommu()
2835 struct amd_iommu *iommu; in early_enable_iommus() local
2855 for_each_iommu(iommu) { in early_enable_iommus()
2856 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2857 early_enable_iommu(iommu); in early_enable_iommus()
2868 for_each_iommu(iommu) { in early_enable_iommus()
2869 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2870 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2871 iommu_disable_irtcachedis(iommu); in early_enable_iommus()
2872 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2873 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2874 iommu_enable_ga(iommu); in early_enable_iommus()
2875 iommu_enable_xt(iommu); in early_enable_iommus()
2876 iommu_enable_irtcachedis(iommu); in early_enable_iommus()
2877 iommu_set_device_table(iommu); in early_enable_iommus()
2878 iommu_flush_all_caches(iommu); in early_enable_iommus()
2885 struct amd_iommu *iommu; in enable_iommus_v2() local
2887 for_each_iommu(iommu) { in enable_iommus_v2()
2888 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
2889 iommu_enable_gt(iommu); in enable_iommus_v2()
2897 struct amd_iommu *iommu; in enable_iommus_vapic() local
2899 for_each_iommu(iommu) { in enable_iommus_vapic()
2904 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2908 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in enable_iommus_vapic()
2909 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in enable_iommus_vapic()
2916 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2940 for_each_iommu(iommu) { in enable_iommus_vapic()
2941 if (iommu_init_ga_log(iommu) || in enable_iommus_vapic()
2942 iommu_ga_log_enable(iommu)) in enable_iommus_vapic()
2945 iommu_feature_enable(iommu, CONTROL_GAM_EN); in enable_iommus_vapic()
2947 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); in enable_iommus_vapic()
2962 struct amd_iommu *iommu; in disable_iommus() local
2964 for_each_iommu(iommu) in disable_iommus()
2965 iommu_disable(iommu); in disable_iommus()
2980 struct amd_iommu *iommu; in amd_iommu_resume() local
2982 for_each_iommu(iommu) in amd_iommu_resume()
2983 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
3080 * This is the hardware init function for AMD IOMMU in the system.
3084 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
3212 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
3215 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
3216 ret = iommu_init_irq(iommu); in amd_iommu_enable_interrupts()
3252 /* Don't use IOMMU if there is Stoney Ridge graphics */ in detect_ivrs()
3258 pr_info("Disable IOMMU on Stoney Ridge\n"); in detect_ivrs()
3272 * AMD IOMMU Initialization State Machine
3335 struct amd_iommu *iommu; in state_next() local
3341 for_each_iommu(iommu) in state_next()
3342 iommu_flush_all_caches(iommu); in state_next()
3411 * This is the core init function for AMD IOMMU hardware in the system.
3417 struct amd_iommu *iommu; in amd_iommu_init() local
3424 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
3431 for_each_iommu(iommu) in amd_iommu_init()
3432 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
3451 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
3458 * Early detect code. This code runs at IOMMU detection time in the DMA
3479 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
3486 * Parsing functions for the AMD IOMMU specific kernel command line
3520 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); in parse_amd_iommu_options()
3703 /* CPU page table size should match IOMMU guest page table size */ in amd_iommu_v2_supported()
3720 struct amd_iommu *iommu; in get_amd_iommu() local
3722 for_each_iommu(iommu) in get_amd_iommu()
3724 return iommu; in get_amd_iommu()
3730 * IOMMU EFR Performance Counter support functionality. This code allows
3731 * access to the IOMMU PC functionality.
3737 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3739 if (iommu) in amd_iommu_pc_get_max_banks()
3740 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3754 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3756 if (iommu) in amd_iommu_pc_get_max_counters()
3757 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3763 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3769 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3773 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3774 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3780 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3781 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3789 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3790 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3792 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3794 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3801 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3803 if (!iommu) in amd_iommu_pc_get_reg()
3806 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3809 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3811 if (!iommu) in amd_iommu_pc_set_reg()
3814 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()
3821 * The SNP support requires that IOMMU must be enabled, and is in amd_iommu_snp_enable()
3825 pr_err("SNP: IOMMU is disabled or configured in passthrough mode, SNP cannot be supported"); in amd_iommu_snp_enable()
3831 * affect how IOMMU driver sets up data structures and configures in amd_iommu_snp_enable()
3832 * IOMMU hardware. in amd_iommu_snp_enable()
3835 pr_err("SNP: Too late to enable SNP for IOMMU.\n"); in amd_iommu_snp_enable()
3845 /* Enforce IOMMU v1 pagetable when SNP is enabled. */ in amd_iommu_snp_enable()
3847 pr_warn("Force to using AMD IOMMU v1 page table due to SNP\n"); in amd_iommu_snp_enable()