Home
last modified time | relevance | path

Searched full:iddq (Results 1 – 14 of 14) sorted by relevance

/openbmc/u-boot/arch/arm/dts/
H A Dtegra210-p2371-2180.dts44 nvidia,iddq = <0>;
50 nvidia,iddq = <0>;
56 nvidia,iddq = <0>;
63 nvidia,iddq = <0>;
69 nvidia,iddq = <0>;
H A Dtegra124-jetson-tk1.dts286 nvidia,iddq = <0>;
293 nvidia,iddq = <0>;
299 nvidia,iddq = <0>;
H A Dtegra124-cei-tk1-som.dts287 nvidia,iddq = <0>;
294 nvidia,iddq = <0>;
H A Dtegra124-apalis.dts1935 nvidia,iddq = <0>;
1942 nvidia,iddq = <0>;
1948 nvidia,iddq = <0>;
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.c110 group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1); in tegra_xusb_padctl_group_parse_dt()
178 * Set IDDQ if supported on the lane and specified in the in tegra_xusb_padctl_group_apply()
181 if (lane->iddq > 0 && group->iddq >= 0) { in tegra_xusb_padctl_group_apply()
182 if (group->iddq != 0) in tegra_xusb_padctl_group_apply()
183 value &= ~(1 << lane->iddq); in tegra_xusb_padctl_group_apply()
185 value |= 1 << lane->iddq; in tegra_xusb_padctl_group_apply()
H A Dxusb-padctl-common.h23 unsigned int iddq; member
46 int iddq; member
59 int iddq; member
H A Dcpu.c160 /* Disable IDDQ */ in pllx_set_iddq()
165 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__, in pllx_set_iddq()
/openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/
H A DCRP0.interface.yaml31 IQ keyword.IDDQ (Chip Level, EX Level) data.
35 TC keyword.IDDQ (Chip Level, EX Level) data.
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dxusb-padctl.c88 .iddq = _iddq, \
H A Dclock.c843 /* clear IDDQ before accessing any other PLLC registers */ in clock_early_init()
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dxusb-padctl.c68 .iddq = _iddq, \
H A Dclock.c1014 /* PLLC_MISC1: Turn IDDQ off. NOTE: T210 PLLC_MISC_1 maps to pll_misc */ in clock_early_init()
/openbmc/u-boot/drivers/pci/
H A Dpci_tegra.c677 /* override IDDQ to 1 on all 4 lanes */ in tegra_pcie_phy_enable()
710 /* turn off IDDQ override */ in tegra_pcie_phy_enable()
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c663 /* clear IDDQ before accessing any other PLLC registers */ in clock_early_init()