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/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
181 compatible = "sifive,fu540-c000-prci";
187 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
195 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
204 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
212 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
224 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
235 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
[all …]
H A Dhifive-unleashed-a00.dts4 #include "fu540-c000.dtsi"
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
15 "sifive,fu540";
/openbmc/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu540-prci.yaml5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
14 On the FU540 family of SoCs, most system-wide clock and reset integration
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26 const: sifive,fu540-c000-prci
55 compatible = "sifive,fu540-c000-prci";
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 - sifive,fu540-c000-pdma
37 "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
38 SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
67 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml30 - sifive,fu540-c000-pwm
35 compatible strings are "sifive,fu540-c000-pwm" and
37 SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
53 Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
66 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
/openbmc/u-boot/board/sifive/fu540/
H A DMAINTAINERS1 SiFive FU540 BOARD
7 F: board/sifive/fu540/
8 F: include/configs/sifive-fu540.h
H A DKconfig4 default "fu540"
13 default "sifive-fu540"
H A DMakefile5 obj-y += fu540.o
/openbmc/u-boot/drivers/clk/sifive/
H A DKconfig13 bool "PRCI driver for SiFive FU540 SoCs"
18 FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
H A Dfu540-prci.c18 * The FU540 PRCI implements clock and reset control for the SiFive
19 * FU540-C000 chip. This driver assumes that it has sole control
28 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
40 #include <dt-bindings/clk/sifive-fu540-prci.h>
251 * Given a value @r read from an FU540 PRCI PLL configuration register,
592 { .compatible = "sifive,fu540-c000-prci0" },
598 .name = "sifive-fu540-prci",
H A DMakefile5 obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml16 - sifive,fu540-c000-gpio
69 - sifive,fu540-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
81 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
/openbmc/linux/drivers/clk/sifive/
H A Dfu540-prci.h8 * The FU540 PRCI implements clock and reset control for the SiFive
9 * FU540-C000 chip. This driver assumes that it has sole control
16 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
25 #include <dt-bindings/clock/sifive-fu540-prci.h>
H A DKconfig20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml21 - sifive,fu540-c000-spi
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
29 as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
76 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml25 - sifive,fu540-c000-ccache
37 - sifive,fu540-c000-ccache
46 - const: sifive,fu540-c000-ccache
157 compatible = "sifive,fu540-c000-ccache", "cache";
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml21 - sifive,fu540-c000-uart
56 #include <dt-bindings/clock/sifive-fu540-prci.h>
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml33 - sifive,fu540-c000-clint # SiFive FU540
70 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
/openbmc/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.h3 * SiFive FU540 Platform DMA driver
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
66 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
165 const: sifive,fu540-c000-gem
/openbmc/linux/Documentation/devicetree/bindings/riscv/
H A Dsifive.yaml24 - const: sifive,fu540-c000
25 - const: sifive,fu540
/openbmc/linux/Documentation/devicetree/bindings/sifive/
H A Dsifive-blocks-ip-versioning.txt30 "sifive,fu540-c000-uart". This way, if SoC-specific
38 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
/openbmc/u-boot/arch/riscv/
H A DKconfig18 bool "Support SiFive FU540 Board"
25 source "board/sifive/fu540/Kconfig"
/openbmc/qemu/include/hw/misc/
H A Dsifive_u_prci.h35 * Current FU540-C000 manual says ready bit is at bit 29, but
87 * These values are from sifive-fu540-prci.h in the Linux kernel.
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dopencores,i2c-ocores.yaml22 - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC

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