| /openbmc/linux/Documentation/devicetree/bindings/fpga/ |
| H A D | fpga-region.txt | 1 FPGA Region Device Tree Binding
9 - FPGA Region
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
22 This device tree binding document hits some of the high points of FPGA usage and
23 attempts to include terminology used by both major FPGA manufacturers. This
24 document isn't a replacement for any manufacturers specifications for FPGA
32 * The entire FPGA is programmed.
35 * A section of an FPGA is reprogrammed while the rest of the FPGA is not
37 * Not all FPGA's support PR.
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| /openbmc/linux/drivers/fpga/ |
| H A D | Kconfig | 3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
45 FPGA manager driver support for Altera Arria/Cyclone/Stratix
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| H A D | of-fpga-region.c | 3 * FPGA Region - Device Tree support for FPGA programming under Linux
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
33 * Return: FPGA Region struct or NULL
41 * of_fpga_region_get_mgr - get reference for FPGA manager
42 * @np: device node of FPGA region
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| H A D | fpga-mgr.c | 3 * FPGA Manager Core
12 #include <linux/fpga/fpga-mgr.h>
56 * After all the FPGA image has been written, do the device specific steps to
57 * finish and set the FPGA into operating mode.
68 dev_err(&mgr->dev, "Error after writing image data to FPGA\n"); in fpga_mgr_write_complete()
104 * fpga_image_info_alloc - Allocate an FPGA image info struct
128 * fpga_image_info_free - Free an FPGA image info struct
129 * @info: FPGA image info struct to free
148 * Call the low level driver's parse_header function with entire FPGA image
161 dev_err(&mgr->dev, "Bitstream data outruns FPGA image\n"); in fpga_mgr_parse_header_mapped()
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| H A D | fpga-region.c | 3 * FPGA Region - Support for FPGA programming under Linux
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
36 * fpga_region_get - get an exclusive reference to an fpga region
37 * @region: FPGA Region struct
51 dev_dbg(dev, "%s: FPGA Region already in use\n", __func__); in fpga_region_get()
70 * @region: FPGA region
84 * fpga_region_program_fpga - program FPGA
86 * @region: FPGA region
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| H A D | fpga-bridge.c | 3 * FPGA Bridge Framework Driver
8 #include <linux/fpga/fpga-bridge.h>
25 * @bridge: FPGA bridge
43 * @bridge: FPGA bridge
81 * of_fpga_bridge_get - get an exclusive reference to an fpga bridge
83 * @np: node pointer of an FPGA bridge.
84 * @info: fpga image specific information.
89 * * -ENODEV if @np is not an FPGA Bridge or can't take parent driver refcount.
115 * fpga_bridge_get - get an exclusive reference to an fpga bridge
116 * @dev: parent device that fpga bridge was registered with
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| H A D | Makefile | 3 # Makefile for the fpga framework and fpga manager drivers.
6 # Core FPGA Manager Framework
7 obj-$(CONFIG_FPGA) += fpga-mgr.o
9 # FPGA Manager Drivers
17 obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
19 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
20 obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
21 obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
28 # FPGA Secure Update Drivers
31 # FPGA Bridge Drivers
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| /openbmc/linux/Documentation/driver-api/fpga/ |
| H A D | fpga-region.rst | 1 FPGA Region
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
22 An fpga-region can be set up to know the following things:
24 * which FPGA manager to use to do the programming
28 Additional info needed to program the FPGA image is passed in the struct
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| H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
22 The struct fpga_image_info specifies what FPGA image to program. It is
26 How to program an FPGA using a region
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| H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
29 includes the framework in fpga-mgr.c and the low level drivers that
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| H A D | fpga-mgr.rst | 1 FPGA Manager
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
26 To add another FPGA manager, write a driver that implements a set of ops. The
53 mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
80 do the programming sequence for this particular FPGA. These ops return 0 for
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| H A D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
13 the module that registers the FPGA bridge as the owner.
15 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
18 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
21 .. kernel-doc:: drivers/fpga/fpga-bridge.c
24 .. kernel-doc:: drivers/fpga/fpga-bridge.c
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| /openbmc/u-boot/drivers/fpga/ |
| H A D | Kconfig | 1 menu "FPGA support"
3 config FPGA config
7 bool "Enable Altera FPGA drivers"
8 select FPGA
10 Say Y here to enable the Altera FPGA driver
12 This provides basic infrastructure to support Altera FPGA devices.
13 Enable Altera FPGA specific functions which includes bitstream
14 (in BIT format), fpga and device validation.
17 bool "Enable Gen5 and Arria10 common FPGA drivers"
20 Say Y here to enable the Gen5 and Arria10 common FPGA driver
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| H A D | socfpga_gen5.c | 29 /* Start the FPGA programming by initialize the FPGA Manager */
74 /* To enable FPGA Manager configuration */ in fpgamgr_program_init()
77 /* To enable FPGA Manager drive over configuration line */ in fpgamgr_program_init()
80 /* Put FPGA into reset phase */ in fpgamgr_program_init()
83 /* (1) wait until FPGA enter reset phase */ in fpgamgr_program_init()
91 puts("FPGA: Could not reset\n"); in fpgamgr_program_init()
95 /* Release FPGA from reset phase */ in fpgamgr_program_init()
98 /* (2) wait until FPGA enter configuration phase */ in fpgamgr_program_init()
106 puts("FPGA: Could not configure\n"); in fpgamgr_program_init()
119 /* Ensure the FPGA entering config done */
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| /openbmc/u-boot/test/py/tests/ |
| H A D | test_fpga.py | 69 pytest.skip('No FPGA to test')
95 ###### FPGA FAIL test ######
96 expected_usage = 'fpga - loadable FPGA image support'
101 # Test non valid fpga subcommand
102 expected = 'fpga: non existing command'
103 output = u_boot_console.run_command('fpga broken 0')
110 output = u_boot_console.run_command('fpga')
114 ###### FPGA DUMP tests ######
122 # Same as above but via "fpga" variable
125 ###### FPGA INFO tests ######
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| /openbmc/u-boot/board/gdsys/common/ |
| H A D | cmd_ioloop.c | 55 static void io_check_status(unsigned int fpga, u16 status, bool silent) in io_check_status() argument
62 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
67 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
88 static void io_send(unsigned int fpga, unsigned int size) in io_send() argument
99 FPGA_SET_REG(fpga, ep.transmit_data, *p++); in io_send()
102 FPGA_SET_REG(fpga, ep.transmit_data, k); in io_send()
104 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_send()
110 static void io_receive(unsigned int fpga) in io_receive() argument
115 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_receive()
123 FPGA_GET_REG(fpga, ep.receive_data, &rx); in io_receive()
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| /openbmc/linux/include/linux/fpga/ |
| H A D | fpga-mgr.h | 3 * FPGA Framework
18 * enum fpga_mgr_states - fpga framework states
20 * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off
21 * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up
22 * @FPGA_MGR_STATE_RESET: FPGA in reset state
25 * @FPGA_MGR_STATE_PARSE_HEADER: parse FPGA image header
27 * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming
29 * @FPGA_MGR_STATE_WRITE: writing image to FPGA
30 * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA
33 * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating
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| H A D | fpga-bridge.h | 7 #include <linux/fpga/fpga-mgr.h>
12 * struct fpga_bridge_ops - ops for low level FPGA bridge drivers
13 * @enable_show: returns the FPGA bridge's status
14 * @enable_set: set an FPGA bridge as enabled or disabled
15 * @fpga_bridge_remove: set FPGA into a specific state during driver remove
26 * struct fpga_bridge_info - collection of parameters an FPGA Bridge
27 * @name: fpga bridge name
28 * @br_ops: pointer to structure of fpga bridge ops
29 * @priv: fpga bridge private data
43 * struct fpga_bridge - FPGA bridge structure
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| H A D | fpga-region.h | 7 #include <linux/fpga/fpga-mgr.h>
8 #include <linux/fpga/fpga-bridge.h>
13 * struct fpga_region_info - collection of parameters an FPGA Region
14 * @mgr: fpga region manager
15 * @compat_id: FPGA region id for compatibility check.
16 * @priv: fpga region private data
32 * struct fpga_region - FPGA Region structure
33 * @dev: FPGA Region device
35 * @bridge_list: list of FPGA bridges specified in region
36 * @mgr: FPGA manager
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| /openbmc/linux/Documentation/devicetree/bindings/board/ |
| H A D | fsl-board.txt | 20 * Freescale on-board FPGA
22 This is the memory-mapped registers for on board FPGA.
26 indicating the type of FPGA. Example:
27 "fsl,<board>-fpga", "fsl,fpga-pixis", or
28 "fsl,<board>-fpga", "fsl,fpga-qixis"
29 - reg: should contain the address and the length of the FPGA register set.
37 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
46 compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
50 * Freescale on-board FPGA connected on I2C bus
52 Some Freescale boards like BSC9132QDS have on board FPGA connected on
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-fpga-manager | 1 What: /sys/class/fpga_manager/<fpga>/name
5 Description: Name of low level fpga manager driver.
7 What: /sys/class/fpga_manager/<fpga>/state
11 Description: Read fpga manager state as a string.
13 wrong during FPGA programming (something that the driver can't
18 This is a superset of FPGA states and fpga manager driver
19 states. The fpga manager driver is walking through these steps
20 to get the FPGA into a known operating state. It's a sequence,
21 though some steps may get skipped. Valid FPGA states will vary
25 * power off = FPGA power is off
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
22 -- Host never reads from the FPGA
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
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| /openbmc/u-boot/drivers/misc/ |
| H A D | gdsys_soc.c | 15 * @fpga: The gdsys IHS FPGA this bus is associated with
18 struct udevice *fpga; member
26 int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga) in gdsys_soc_get_fpga() argument
42 *fpga = bus_priv->fpga; in gdsys_soc_get_fpga()
50 struct udevice *fpga; in gdsys_soc_probe() local
51 int res = uclass_get_device_by_phandle(UCLASS_MISC, dev, "fpga", in gdsys_soc_probe()
52 &fpga); in gdsys_soc_probe()
54 debug("%s: Could not find 'fpga' phandle\n", dev->name); in gdsys_soc_probe()
59 debug("%s: Could not get FPGA device\n", dev->name); in gdsys_soc_probe()
63 priv->fpga = fpga; in gdsys_soc_probe()
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| /openbmc/u-boot/board/spear/x600/ |
| H A D | fpga.c | 16 * FPGA program pin configuration on X600:
21 * FPGA.
27 * Set the active-low FPGA reset signal.
32 * On x600 we have no means to toggle the FPGA reset signal in fpga_reset()
38 * Set the FPGA's active-low SelectMap program line to the specified level
42 debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); in fpga_pgm_fn()
50 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
60 * On x600, the FPGA INIT signal is not connected to the SoC. in fpga_init_fn()
73 * Test the state of the active-high FPGA DONE pin
92 * FPGA pre-configuration function. Just make sure that
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| /openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/ |
| H A D | sdk.h | 42 * This header defines the in-kernel API for Innova FPGA client drivers.
51 * @MLX5_FPGA_ACCESS_TYPE_I2C: Use the slow CX-FPGA I2C bus
87 * @conn: FPGA Connection this packet was sent to
88 * @fdev: FPGA device this packet was sent to
98 * struct mlx5_fpga_conn_attr - FPGA connection attributes
122 * mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection
123 * @fdev: The FPGA device
126 * Sets up a new FPGA SBU connection with the specified attributes.
140 * mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection
141 * @conn: The FPGA SBU connection to destroy
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