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/openbmc/linux/arch/arm/kernel/
H A Dfiq.c3 * linux/arch/arm/kernel/fiq.c
8 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
10 * FIQ support re-written by Russell King to be more generic
12 * We now properly support a method by which the FIQ handlers can
14 * the FIQ vector itself.
17 * 1. Owner A claims FIQ:
22 * - enables FIQ.
23 * 3. Owner B claims FIQ:
31 * - enables FIQ.
32 * 5. Owner B releases FIQ:
[all …]
H A Dfiqasm.S4 * Derived from code originally in linux/arch/arm/kernel/fiq.c:
10 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
12 * FIQ support re-written by Russell King to be more generic
21 * Taking an interrupt in FIQ mode is death, so both these functions
28 msr cpsr_c, r2 @ select FIQ mode
41 msr cpsr_c, r2 @ select FIQ mode
/openbmc/linux/fs/fuse/
H A Ddev.c195 u64 fuse_get_unique(struct fuse_iqueue *fiq) in fuse_get_unique() argument
197 fiq->reqctr += FUSE_REQ_ID_STEP; in fuse_get_unique()
198 return fiq->reqctr; in fuse_get_unique()
208 * A new request is available, wake fiq->waitq
210 static void fuse_dev_wake_and_unlock(struct fuse_iqueue *fiq) in fuse_dev_wake_and_unlock() argument
211 __releases(fiq->lock) in fuse_dev_wake_and_unlock()
213 wake_up(&fiq->waitq); in fuse_dev_wake_and_unlock()
214 kill_fasync(&fiq->fasync, SIGIO, POLL_IN); in fuse_dev_wake_and_unlock()
215 spin_unlock(&fiq->lock); in fuse_dev_wake_and_unlock()
225 static void queue_request_and_unlock(struct fuse_iqueue *fiq, in queue_request_and_unlock() argument
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.c3 * Amstrad E3 FIQ handling
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
27 #include "ams-delta-fiq.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
36 * The FIQ and IRQ isrs can both read and write it.
38 * followed by the circular buffer where the FIQ isr stores
40 * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
60 * until the IRQ counter catches the FIQ incremented interrupt counter. in deferred_fiq()
[all …]
H A Dams-delta-fiq-handler.S3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
14 #include <linux/platform_data/ams-delta-fiq.h>
22 #include "ams-delta-fiq.h"
93 @ FIQ intrrupt handler
100 beq exit @ none - spurious FIQ? exit
104 mov r8, #2 @ reset FIQ agreement
114 subs pc, lr, #4 @ return from FIQ
138 @ Keyboard clock FIQ mode interrupt handler
222 @ Hook switch interrupt FIQ mode simple handler
239 @ Modem FIQ mode interrupt handler stub
[all …]
H A Dirq.c97 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
98 * mailing list threads on FIQ handlers if you are planning to
99 * add a FIQ handler for OMAP.
101 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) in omap_irq_set_cfg() argument
107 /* FIQ is only available on bank 0 interrupts */ in omap_irq_set_cfg()
108 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
109 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); in omap_irq_set_cfg()
H A Dams-delta-fiq.h4 * arch/arm/mach-omap1/ams-delta-fiq.h
6 * Taken from the original Amstrad modifications to fiq.h
22 * Interrupt number used for passing control from FIQ to IRQ.
/openbmc/linux/arch/arm/include/asm/
H A Dfiq.h3 * arch/arm/include/asm/fiq.h
5 * Support for FIQ on ARM architectures.
9 * NOTE: The FIQ mode registers are not magically preserved across
28 * reacquire FIQ
40 extern void enable_fiq(int fiq);
41 extern void disable_fiq(int fiq);
H A Decard.h104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
147 void __iomem *fiqaddr; /* address of FIQ register */
149 unsigned char fiqmask; /* FIQ mask */
154 void *fiq_data; /* Data for use for FIQ by card */
160 CONST unsigned int fiq; /* FIQ number (for request_irq) */ member
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic2.yaml27 This device also represents the FIQ interrupt sources on platforms using AIC,
29 FIQ-based Fast IPIs.
47 - 1: FIQ
79 FIQ affinity can be expressed as a single "affinities" node,
80 containing a set of sub-nodes, one per FIQ with a non-default
87 apple,fiq-index:
89 The interrupt number specified as a FIQ, and for which
101 - apple,fiq-index
H A Dapple,aic.yaml31 This device also represents the FIQ interrupt sources on platforms using AIC,
50 - 1: FIQ
77 FIQ affinity can be expressed as a single "affinities" node,
78 containing a set of sub-nodes, one per FIQ with a non-default
85 apple,fiq-index:
87 The interrupt number specified as a FIQ, and for which
98 - apple,fiq-index
H A Dcirrus,clps711x-intc.txt14 1: BLINT Battery low (FIQ)
15 3: MCINT Media changed (FIQ)
33 32: DAIINT DAI interface (FIQ)
H A Dst,stih407-irq-syscfg.yaml32 st,fiq-device:
50 - st,fiq-device
62 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
/openbmc/linux/drivers/irqchip/
H A Dirq-apple-aic.c36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
39 * - <1 nr flags> - FIQ #nr
163 * IMP-DEF sysregs that control FIQ sources
182 /* Guest timer FIQ enable register */
216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
453 * FIQ irqchip
522 * the FIQ source state without having to peek down into sources... in aic_handle_fiq()
531 * Since not dealing with any of these results in a FIQ storm, in aic_handle_fiq()
580 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); in aic_handle_fiq()
592 .name = "AIC-FIQ",
[all …]
H A Dirq-ixp4xx.c28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
215 /* Route all sources to IRQ instead of FIQ */ in ixp4xx_irq_setup()
222 /* Route upper 32 sources to IRQ instead of FIQ */ in ixp4xx_irq_setup()
H A Dirq-st.c89 /* Select IRQ/FIQ channel for device. */ in st_irq_xlate()
110 channels = of_property_count_u32_elems(np, "st,fiq-device"); in st_irq_syscfg_enable()
112 dev_err(&pdev->dev, "st,enable-fiq-device must have 2 elems\n"); in st_irq_syscfg_enable()
123 of_property_read_u32_index(np, "st,fiq-device", i, &device); in st_irq_syscfg_enable()
/openbmc/linux/arch/arm64/mm/
H A Dtrans_pgd-asm.S43 invalid_vector hyp_stub_el2t_fiq_invalid // FIQ EL2t
48 invalid_vector hyp_stub_el2h_fiq_invalid // FIQ EL2h
53 invalid_vector hyp_stub_el1_fiq_invalid // FIQ 64-bit EL1
58 invalid_vector hyp_stub_32b_el1_fiq_invalid // FIQ 32-bit EL1
/openbmc/linux/include/linux/irqchip/
H A Dirq-bcm2836.h13 * next 2 bits identify the CPU that the GPU FIQ goes to.
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
37 /* Same status bits as above, but for FIQ. */
/openbmc/qemu/hw/intc/
H A Domap_intc.c35 uint32_t fiq; member
74 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); in omap_inth_sir_update()
96 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); in omap_inth_update()
202 ((bank->fiq >> i) & 1); in omap_inth_read()
290 bank->fiq &= ~(1 << i); in omap_inth_write()
291 bank->fiq |= (value & 1) << i; in omap_inth_write()
324 s->bank[i].fiq = 0x00000000; in omap_inth_reset()
H A Dbcm2836_control.c67 /* deliver a FIQ */ in deliver_local()
100 * cores' IRQ/FIQ; this is distinct from the per-CPU timer in bcm2836_control_update()
136 qemu_set_irq(s->fiq[i], s->fiqsrc[i] != 0); in bcm2836_control_update()
355 /* IRQ and FIQ inputs from upstream bcm2835 controller */ in bcm2836_control_init()
357 qdev_init_gpio_in_named(dev, bcm2836_control_set_gpu_fiq, "gpu-fiq", 1); in bcm2836_control_init()
361 qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES); in bcm2836_control_init()
/openbmc/u-boot/arch/arm/lib/
H A Dinterrupts_64.c67 * do_bad_fiq handles the impossible case in the Fiq vector.
72 printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr); in do_bad_fiq()
111 * do_fiq handles the Fiq exception.
116 printf("\"Fiq\" handler, esr 0x%08x\n", esr); in do_fiq()
/openbmc/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dhandlers.S110 HANDLER_INVALID // FIQ EL1t
115 HANDLER el1h_fiq // FIQ EL1h
120 HANDLER el0_fiq_64 // FIQ 64-bit EL0
125 HANDLER el0_fiq_32 // FIQ 32-bit EL0
/openbmc/linux/arch/arm64/kernel/
H A Dentry.S523 kernel_ventry 1, t, 64, fiq // FIQ EL1t
528 kernel_ventry 1, h, 64, fiq // FIQ EL1h
533 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
538 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
591 entry_handler 1, t, 64, fiq
596 entry_handler 1, h, 64, fiq
601 entry_handler 0, t, 64, fiq
606 entry_handler 0, t, 32, fiq
789 kernel_ventry 1, t, 64, fiq // FIQ EL1h
794 kernel_ventry 1, h, 64, fiq // FIQ EL1h
H A Dhyp-stub.S27 ventry el2_fiq_invalid // FIQ EL2t
32 ventry el2_fiq_invalid // FIQ EL2h
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
/openbmc/linux/arch/arm/mach-rpc/
H A Ddma.c17 #include <asm/fiq.h>
262 unsigned int fiq; member
290 printk("floppydma: couldn't claim FIQ.\n"); in floppy_enable_dma()
296 enable_fiq(fdma->fiq); in floppy_enable_dma()
302 disable_fiq(fdma->fiq); in floppy_disable_dma()
339 .fiq = FIQ_FLOPPYDATA,

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