Searched full:every (Results 1 – 25 of 3977) sorted by relevance
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9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol…12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old…15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…[all …]
9 …": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ i…12 …": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ i…15 …on": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ i…18 …on": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ i…21 … operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ i…24 … operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ i…27 …ion": "No operation issued due to the backend interlock.This event counts every cycle that issue i…30 …ion": "No operation issued due to the backend interlock.This event counts every cycle that issue i…33 …"No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue i…36 …"No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue i…[all …]
21 …: "No operation issued due to the frontend, cache miss. This event counts every cycle that the Dat…24 …: "No operation issued due to the frontend, cache miss. This event counts every cycle that the Dat…27 …n": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU…30 …n": "No operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU…39 …on": "No operation issued due to the backend interlock. This event counts every cycle where the is…42 …on": "No operation issued due to the backend interlock. This event counts every cycle where the is…45 …operation issued due to the backend, address interlock. This event counts every cycle where the is…48 …operation issued due to the backend, address interlock. This event counts every cycle where the is…51 …ackend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there …54 …ackend, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there …[all …]
3 …"BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum …7 …"PublicDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum…12 "BriefDescription": "Counts every read and write request entering the Memory Controller 0.",16 …"PublicDescription": "Counts every read and write request entering the Memory Controller 0 (sum of…21 …"BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum…25 …"PublicDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (su…30 …"BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum …34 …"PublicDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum…39 "BriefDescription": "Counts every read and write request entering the Memory Controller 1.",43 …"PublicDescription": "Counts every read and write request entering the Memory Controller 1 (sum of…[all …]
16 "Every"19 "Every": "Every day of the week.", string29 …"Every": "This value indicates that every day of the week has been selected. When used in array p… string49 "Every"55 "Every": "Every month of the year.", string67 …"Every": "This value indicates that every month of the year has been selected. When used in array… string92 … of the month when scheduled occurrences are enabled. `0` indicates that every day of the month i…
17 Every, enumerator34 Every, enumerator46 {DayOfWeek::Every, "Every"},63 {MonthOfYear::Every, "Every"},
37 # update every = 155 # dbengine tier 1 update every iterations = 6056 # dbengine tier 2 update every iterations = 60103 # train every = 10800135 # run at least every seconds = 10151 # accept a streaming request every seconds = 0181 # registry save db every new entries = 1000000196 # update every = 1209 # check for new plugins every = 60224 # update every (flushInterval) = 1[all …]
265 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…279 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…294 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …300 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…307 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…314 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…321 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…328 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…335 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…350 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …[all …]
3 …"BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all…11 …"BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRA…19 …"BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of al…27 …"BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all…35 …"BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRA…43 …"BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of al…
347 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…361 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…368 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…375 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by …381 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…388 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…395 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…402 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…409 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…416 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba…[all …]
3 …"BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum …7 …"PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum …12 …"BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum …20 …"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum o…24 …"PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all c…29 …"BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum …
18 # 1 - every 20 minutes19 # 2 - every 30 minutes20 # 3 - every hour21 # 4 - every midnight
40 * 16 bytes per entry, one entry for every hop (REG_CAPS)49 * 16 bytes per entry, one entry for every hop (REG_CAPS)59 * 32 bytes per entry, one entry for every hop (REG_CAPS)67 * 32 bytes per entry, one entry for every hop (REG_CAPS)80 * Every bitfield contains one bit for every hop (REG_CAPS).90 * Both bitfields contains one bit for every hop (REG_CAPS). To
80 * increment only every few clock cycle). in gen11_read_clock_frequency()102 * increment only every few clock cycle). in gen9_read_clock_frequency()118 * rolling over every 1.5 hours). in gen6_read_clock_frequency()126 * 63:32 increments every 1000 ns in gen5_read_clock_frequency()135 * 63:20 increments every 1/4 ns in g4x_read_clock_frequency()138 * -> 63:32 increments every 1024 ns in g4x_read_clock_frequency()148 * "The value in this register increments once every 16 in gen4_read_clock_frequency()
66 * This function must be modified for every new Octeon board.69 * fact that every Octeon board receives a unique board type84 * This function must be modified for every new Octeon board.87 * fact that every Octeon board receives a unique board type106 * This function must be modified for every new Octeon board.109 * fact that every Octeon board receives a unique board type
6 Every rpmsg device is a communication channel with a remote18 Every rpmsg device is a communication channel with a remote36 Every rpmsg device is a communication channel with a remote58 Every rpmsg device is a communication channel with a remote82 Every rpmsg device is a communication channel with a remote
6 Exposes magic errors: every node starts with a magic number.18 Exposes node errors. Every node embeds its type.30 Exposes crc errors: every node embeds a crc checksum.
109 in the Makefile. Think of this as applying ``__no_sanitize_memory`` to every128 KMSAN associates a metadata byte (also called shadow byte) with every byte of146 propagated into all the operations which use that value. For every instruction163 Every four bytes of kernel memory also have a so-called origin mapped to them.165 value was created. Every origin is associated with either the full allocation172 shadow. For every instruction that takes one or more values, the origin of the188 same four-byte chunk. In this case every write to either variable updates the215 To ease debugging, KMSAN creates a new origin for every store of an229 For every memory access the compiler emits a call to a function that returns a243 The compiler makes sure that for every loaded value its shadow and origin[all …]
27 the event types in the trace file; it simply prints every available91 to every event as arguments but are available as library functions.107 The above provides the basics needed to directly access every field of108 every event in a trace, which covers 90% of what you need to know to114 Every perf script Perl script should start by setting up a Perl module129 Aside from the event handler functions discussed above, every script196 $context variable passed into every event handler as the second
74 every time a system call occurs in the system. Our script will do79 - we could enable every event under the tracing/events/syscalls102 The options basically say to collect data for every syscall event161 path append which every perf script script should include.169 every event in the 'perf record' output. The handler functions take176 generated for every script. The first, trace_unhandled(), is called177 every time the script finds an event in the perf.data file that206 Of course, for this script, we're not interested in printing every234 store that information; every time the sys_enter() handler is called,421 the event types in the trace file; it simply prints every available[all …]
67 a flood of mmap system calls for every malloc(4k). Optimizing userland250 Attempt to allocate huge pages every time we need a new page;312 is incremented every time a huge page is successfully335 is incremented every time a file huge page is successfully348 is incremented every time a file huge page is mapped into352 is incremented every time a huge page is split into base368 is incremented every time a PMD split into table of PTEs.374 is incremented every time a huge zero page used for thp is375 successfully allocated. Note, it doesn't count every map of383 is incremented every time a huge page is swapout in one[all …]
15 # every $HTX_INTERVAL.29 # Script that configures every network port when connected to a loop. This64 [Documentation] Stress every controller connected via PCI in an OS with65 ... every resource available (CPU, RAM, storage, ethernet controllers,
26 functions. Every EPC device present in the system will have an entry in27 the *controllers* directory and every EPF driver present in the system38 Every registered EPF driver will be listed in controllers directory. The54 Every <EPF device> directory consists of the following entries that can be94 Every registered EPC device will be listed in controllers directory. The