1*5497b23eSShunsuke Nakamura[
2*5497b23eSShunsuke Nakamura  {
3*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts the occurrence count of the micro-operation split.",
4*5497b23eSShunsuke Nakamura    "EventCode": "0x139",
5*5497b23eSShunsuke Nakamura    "EventName": "UOP_SPLIT",
6*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts the occurrence count of the micro-operation split."
7*5497b23eSShunsuke Nakamura  },
8*5497b23eSShunsuke Nakamura  {
9*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access.",
10*5497b23eSShunsuke Nakamura    "EventCode": "0x180",
11*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_L2_MISS",
12*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no operation was committed because the oldest and uncommitted load/store/prefetch operation waits for memory access."
13*5497b23eSShunsuke Nakamura  },
14*5497b23eSShunsuke Nakamura  {
15*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access.",
16*5497b23eSShunsuke Nakamura    "EventCode": "0x181",
17*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_L2_MISS_EX",
18*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for memory access."
19*5497b23eSShunsuke Nakamura  },
20*5497b23eSShunsuke Nakamura  {
21*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.",
22*5497b23eSShunsuke Nakamura    "EventCode": "0x182",
23*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_L1_MISS",
24*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access."
25*5497b23eSShunsuke Nakamura  },
26*5497b23eSShunsuke Nakamura  {
27*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.",
28*5497b23eSShunsuke Nakamura    "EventCode": "0x183",
29*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_L1_MISS_EX",
30*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access."
31*5497b23eSShunsuke Nakamura  },
32*5497b23eSShunsuke Nakamura  {
33*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.",
34*5497b23eSShunsuke Nakamura    "EventCode": "0x184",
35*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT",
36*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."
37*5497b23eSShunsuke Nakamura  },
38*5497b23eSShunsuke Nakamura  {
39*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.",
40*5497b23eSShunsuke Nakamura    "EventCode": "0x185",
41*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_EX",
42*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."
43*5497b23eSShunsuke Nakamura  },
44*5497b23eSShunsuke Nakamura  {
45*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.",
46*5497b23eSShunsuke Nakamura    "EventCode": "0x186",
47*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_PFP_BUSY",
48*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port."
49*5497b23eSShunsuke Nakamura  },
50*5497b23eSShunsuke Nakamura  {
51*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.",
52*5497b23eSShunsuke Nakamura    "EventCode": "0x187",
53*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_PFP_BUSY_EX",
54*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation."
55*5497b23eSShunsuke Nakamura  },
56*5497b23eSShunsuke Nakamura  {
57*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.",
58*5497b23eSShunsuke Nakamura    "EventCode": "0x188",
59*5497b23eSShunsuke Nakamura    "EventName": "LD_COMP_WAIT_PFP_BUSY_SWPF",
60*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction."
61*5497b23eSShunsuke Nakamura  },
62*5497b23eSShunsuke Nakamura  {
63*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction.",
64*5497b23eSShunsuke Nakamura    "EventCode": "0x189",
65*5497b23eSShunsuke Nakamura    "EventName": "EU_COMP_WAIT",
66*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction."
67*5497b23eSShunsuke Nakamura  },
68*5497b23eSShunsuke Nakamura  {
69*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.",
70*5497b23eSShunsuke Nakamura    "EventCode": "0x18A",
71*5497b23eSShunsuke Nakamura    "EventName": "FL_COMP_WAIT",
72*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction."
73*5497b23eSShunsuke Nakamura  },
74*5497b23eSShunsuke Nakamura  {
75*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.",
76*5497b23eSShunsuke Nakamura    "EventCode": "0x18B",
77*5497b23eSShunsuke Nakamura    "EventName": "BR_COMP_WAIT",
78*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction."
79*5497b23eSShunsuke Nakamura  },
80*5497b23eSShunsuke Nakamura  {
81*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty.",
82*5497b23eSShunsuke Nakamura    "EventCode": "0x18C",
83*5497b23eSShunsuke Nakamura    "EventName": "ROB_EMPTY",
84*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty."
85*5497b23eSShunsuke Nakamura  },
86*5497b23eSShunsuke Nakamura  {
87*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.",
88*5497b23eSShunsuke Nakamura    "EventCode": "0x18D",
89*5497b23eSShunsuke Nakamura    "EventName": "ROB_EMPTY_STQ_BUSY",
90*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full."
91*5497b23eSShunsuke Nakamura  },
92*5497b23eSShunsuke Nakamura  {
93*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.",
94*5497b23eSShunsuke Nakamura    "EventCode": "0x18E",
95*5497b23eSShunsuke Nakamura    "EventName": "WFE_WFI_CYCLE",
96*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction."
97*5497b23eSShunsuke Nakamura  },
98*5497b23eSShunsuke Nakamura  {
99*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only.",
100*5497b23eSShunsuke Nakamura    "EventCode": "0x190",
101*5497b23eSShunsuke Nakamura    "EventName": "_0INST_COMMIT",
102*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only."
103*5497b23eSShunsuke Nakamura  },
104*5497b23eSShunsuke Nakamura  {
105*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that one instruction is committed.",
106*5497b23eSShunsuke Nakamura    "EventCode": "0x191",
107*5497b23eSShunsuke Nakamura    "EventName": "_1INST_COMMIT",
108*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that one instruction is committed."
109*5497b23eSShunsuke Nakamura  },
110*5497b23eSShunsuke Nakamura  {
111*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that two instructions are committed.",
112*5497b23eSShunsuke Nakamura    "EventCode": "0x192",
113*5497b23eSShunsuke Nakamura    "EventName": "_2INST_COMMIT",
114*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that two instructions are committed."
115*5497b23eSShunsuke Nakamura  },
116*5497b23eSShunsuke Nakamura  {
117*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that three instructions are committed.",
118*5497b23eSShunsuke Nakamura    "EventCode": "0x193",
119*5497b23eSShunsuke Nakamura    "EventName": "_3INST_COMMIT",
120*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that three instructions are committed."
121*5497b23eSShunsuke Nakamura  },
122*5497b23eSShunsuke Nakamura  {
123*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that four instructions are committed.",
124*5497b23eSShunsuke Nakamura    "EventCode": "0x194",
125*5497b23eSShunsuke Nakamura    "EventName": "_4INST_COMMIT",
126*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that four instructions are committed."
127*5497b23eSShunsuke Nakamura  },
128*5497b23eSShunsuke Nakamura  {
129*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that only any micro-operations are committed.",
130*5497b23eSShunsuke Nakamura    "EventCode": "0x198",
131*5497b23eSShunsuke Nakamura    "EventName": "UOP_ONLY_COMMIT",
132*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that only any micro-operations are committed."
133*5497b23eSShunsuke Nakamura  },
134*5497b23eSShunsuke Nakamura  {
135*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts every cycle that only the MOVPRFX instruction is committed.",
136*5497b23eSShunsuke Nakamura    "EventCode": "0x199",
137*5497b23eSShunsuke Nakamura    "EventName": "SINGLE_MOVPRFX_COMMIT",
138*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts every cycle that only the MOVPRFX instruction is committed."
139*5497b23eSShunsuke Nakamura  },
140*5497b23eSShunsuke Nakamura  {
141*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts energy consumption per cycle of core.",
142*5497b23eSShunsuke Nakamura    "EventCode": "0x1E0",
143*5497b23eSShunsuke Nakamura    "EventName": "EA_CORE",
144*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts energy consumption per cycle of core."
145*5497b23eSShunsuke Nakamura  },
146*5497b23eSShunsuke Nakamura  {
147*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.",
148*5497b23eSShunsuke Nakamura    "EventCode": "0x230",
149*5497b23eSShunsuke Nakamura    "EventName": "L1HWPF_STREAM_PF",
150*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher."
151*5497b23eSShunsuke Nakamura  },
152*5497b23eSShunsuke Nakamura  {
153*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.",
154*5497b23eSShunsuke Nakamura    "EventCode": "0x231",
155*5497b23eSShunsuke Nakamura    "EventName": "L1HWPF_INJ_ALLOC_PF",
156*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts allocation type prefetch injection requests to L1D cache generated by hardware prefetcher."
157*5497b23eSShunsuke Nakamura  },
158*5497b23eSShunsuke Nakamura  {
159*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher.",
160*5497b23eSShunsuke Nakamura    "EventCode": "0x232",
161*5497b23eSShunsuke Nakamura    "EventName": "L1HWPF_INJ_NOALLOC_PF",
162*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts non-allocation type prefetch injection requests to L1D cache generated by hardware prefetcher."
163*5497b23eSShunsuke Nakamura  },
164*5497b23eSShunsuke Nakamura  {
165*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher.",
166*5497b23eSShunsuke Nakamura    "EventCode": "0x233",
167*5497b23eSShunsuke Nakamura    "EventName": "L2HWPF_STREAM_PF",
168*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts streaming prefetch requests to L2 cache generated by hardware prefecher."
169*5497b23eSShunsuke Nakamura  },
170*5497b23eSShunsuke Nakamura  {
171*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.",
172*5497b23eSShunsuke Nakamura    "EventCode": "0x234",
173*5497b23eSShunsuke Nakamura    "EventName": "L2HWPF_INJ_ALLOC_PF",
174*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts allocation type prefetch injection requests to L2 cache generated by hardware prefetcher."
175*5497b23eSShunsuke Nakamura  },
176*5497b23eSShunsuke Nakamura  {
177*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher.",
178*5497b23eSShunsuke Nakamura    "EventCode": "0x235",
179*5497b23eSShunsuke Nakamura    "EventName": "L2HWPF_INJ_NOALLOC_PF",
180*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts non-allocation type prefetch injection requests to L2 cache generated by hardware prefetcher."
181*5497b23eSShunsuke Nakamura  },
182*5497b23eSShunsuke Nakamura  {
183*5497b23eSShunsuke Nakamura    "PublicDescription": "This event counts prefetch requests to L2 cache generated by the other causes.",
184*5497b23eSShunsuke Nakamura    "EventCode": "0x236",
185*5497b23eSShunsuke Nakamura    "EventName": "L2HWPF_OTHER",
186*5497b23eSShunsuke Nakamura    "BriefDescription": "This event counts prefetch requests to L2 cache generated by the other causes."
187*5497b23eSShunsuke Nakamura  }
188*5497b23eSShunsuke Nakamura]
189