1[ 2 { 3 "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 4 "EventCode": "0xff", 5 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 6 "PerPkg": "1", 7 "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", 8 "UMask": "0x20", 9 "Unit": "imc_free_running_0" 10 }, 11 { 12 "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 13 "EventCode": "0xff", 14 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 15 "PerPkg": "1", 16 "UMask": "0x30", 17 "Unit": "imc_free_running_0" 18 }, 19 { 20 "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", 21 "EventCode": "0xff", 22 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 23 "PerPkg": "1", 24 "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", 25 "UMask": "0x20", 26 "Unit": "imc_free_running_1" 27 }, 28 { 29 "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", 30 "EventCode": "0xff", 31 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 32 "PerPkg": "1", 33 "UMask": "0x30", 34 "Unit": "imc_free_running_1" 35 }, 36 { 37 "BriefDescription": "ACT command for a read request sent to DRAM", 38 "EventCode": "0x24", 39 "EventName": "UNC_M_ACT_COUNT_RD", 40 "PerPkg": "1", 41 "Unit": "iMC" 42 }, 43 { 44 "BriefDescription": "ACT command sent to DRAM", 45 "EventCode": "0x26", 46 "EventName": "UNC_M_ACT_COUNT_TOTAL", 47 "PerPkg": "1", 48 "Unit": "iMC" 49 }, 50 { 51 "BriefDescription": "ACT command for a write request sent to DRAM", 52 "EventCode": "0x25", 53 "EventName": "UNC_M_ACT_COUNT_WR", 54 "PerPkg": "1", 55 "Unit": "iMC" 56 }, 57 { 58 "BriefDescription": "Read CAS command sent to DRAM", 59 "EventCode": "0x22", 60 "EventName": "UNC_M_CAS_COUNT_RD", 61 "PerPkg": "1", 62 "Unit": "iMC" 63 }, 64 { 65 "BriefDescription": "Write CAS command sent to DRAM", 66 "EventCode": "0x23", 67 "EventName": "UNC_M_CAS_COUNT_WR", 68 "PerPkg": "1", 69 "Unit": "iMC" 70 }, 71 { 72 "BriefDescription": "Number of clocks", 73 "EventCode": "0x01", 74 "EventName": "UNC_M_CLOCKTICKS", 75 "PerPkg": "1", 76 "Unit": "iMC" 77 }, 78 { 79 "BriefDescription": "incoming read request page status is Page Empty", 80 "EventCode": "0x1D", 81 "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", 82 "PerPkg": "1", 83 "Unit": "iMC" 84 }, 85 { 86 "BriefDescription": "incoming write request page status is Page Empty", 87 "EventCode": "0x20", 88 "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", 89 "PerPkg": "1", 90 "Unit": "iMC" 91 }, 92 { 93 "BriefDescription": "incoming read request page status is Page Hit", 94 "EventCode": "0x1C", 95 "EventName": "UNC_M_DRAM_PAGE_HIT_RD", 96 "PerPkg": "1", 97 "Unit": "iMC" 98 }, 99 { 100 "BriefDescription": "incoming write request page status is Page Hit", 101 "EventCode": "0x1F", 102 "EventName": "UNC_M_DRAM_PAGE_HIT_WR", 103 "PerPkg": "1", 104 "Unit": "iMC" 105 }, 106 { 107 "BriefDescription": "incoming read request page status is Page Miss", 108 "EventCode": "0x1E", 109 "EventName": "UNC_M_DRAM_PAGE_MISS_RD", 110 "PerPkg": "1", 111 "Unit": "iMC" 112 }, 113 { 114 "BriefDescription": "incoming write request page status is Page Miss", 115 "EventCode": "0x21", 116 "EventName": "UNC_M_DRAM_PAGE_MISS_WR", 117 "PerPkg": "1", 118 "Unit": "iMC" 119 }, 120 { 121 "BriefDescription": "Any Rank at Hot state", 122 "EventCode": "0x19", 123 "EventName": "UNC_M_DRAM_THERMAL_HOT", 124 "PerPkg": "1", 125 "Unit": "iMC" 126 }, 127 { 128 "BriefDescription": "Any Rank at Warm state", 129 "EventCode": "0x1A", 130 "EventName": "UNC_M_DRAM_THERMAL_WARM", 131 "PerPkg": "1", 132 "Unit": "iMC" 133 }, 134 { 135 "BriefDescription": "Incoming read prefetch request from IA.", 136 "EventCode": "0x0A", 137 "EventName": "UNC_M_PREFETCH_RD", 138 "PerPkg": "1", 139 "Unit": "iMC" 140 }, 141 { 142 "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", 143 "EventCode": "0x28", 144 "EventName": "UNC_M_PRE_COUNT_IDLE", 145 "PerPkg": "1", 146 "Unit": "iMC" 147 }, 148 { 149 "BriefDescription": "PRE command sent to DRAM for a read/write request", 150 "EventCode": "0x27", 151 "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", 152 "PerPkg": "1", 153 "Unit": "iMC" 154 }, 155 { 156 "BriefDescription": "Incoming VC0 read request", 157 "EventCode": "0x02", 158 "EventName": "UNC_M_VC0_REQUESTS_RD", 159 "PerPkg": "1", 160 "Unit": "iMC" 161 }, 162 { 163 "BriefDescription": "Incoming VC0 write request", 164 "EventCode": "0x03", 165 "EventName": "UNC_M_VC0_REQUESTS_WR", 166 "PerPkg": "1", 167 "Unit": "iMC" 168 }, 169 { 170 "BriefDescription": "Incoming VC1 read request", 171 "EventCode": "0x04", 172 "EventName": "UNC_M_VC1_REQUESTS_RD", 173 "PerPkg": "1", 174 "Unit": "iMC" 175 }, 176 { 177 "BriefDescription": "Incoming VC1 write request", 178 "EventCode": "0x05", 179 "EventName": "UNC_M_VC1_REQUESTS_WR", 180 "PerPkg": "1", 181 "Unit": "iMC" 182 } 183] 184