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/openbmc/smbios-mdr/include/
H A Dcpu.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
80 {0x1b, "K6-2"},
81 {0x1c, "K6-3"},
84 {0x1f, "K6-2+"},
93 {0x28, "Intel Core Duo processor"},
94 {0x29, "Intel Core Duo mobile processor"},
95 {0x2a, "Intel Core Solo mobile processor"},
97 {0x2c, "Intel Core M processor"},
98 {0x2d, "Intel Core m3 processor"},
99 {0x2e, "Intel Core m5 processor"},
[all …]
/openbmc/u-boot/board/freescale/p1022ds/
H A DREADME2 --------
3 P1022ds is a Low End Dual core platform supporting the P1022 processor
4 of QorIQ series. P1022 is an e500 based dual core SOC.
8 -------------------------------
21 'setenv hwconfig 'audclk:12;tdm' --- error !
22 'setenv hwconfig 'audclk:11;tdm' --- error !
23 'setenv hwconfig 'audclk:10' --- error !
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
[all …]
/openbmc/u-boot/board/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
48 This is the Intel Edison Compute Module. It contains a dual core Intel
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
57 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
58 single-core, single-thread, Intel Pentium processor instrunction set
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig82 The AM335x high performance SOC features a Cortex-A8
83 ARM core and more.
92 The AM335x high performance SOC features a Cortex-A8
93 ARM core and more.
112 The AM43xx high performance SOC features a Cortex-A9
113 ARM core, a quad core PRU-ICSS for industrial Ethernet
114 protocols, dual camera support, optional 3D graphics
130 The AM335x high performance SOC features a Cortex-A8
131 ARM core, a dual core PRU-ICSS for industrial Ethernet
149 Reserved EMIF region start address. Set to "0" to auto-select
[all …]
/openbmc/u-boot/board/freescale/ls1021atwr/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun6i-a31s-sina31s-core.dtsi2 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun6i-a31s.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
50 model = "Sinlinx SinA31s Core Board";
51 compatible = "sinlinx,sina31s", "allwinner,sun6i-a31s";
59 cpu-supply = <&reg_dcdc3>;
[all …]
H A Dsun8i-a23-gt90h-v4.dts4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun8i-a23.dtsi"
45 #include "sun8i-reference-design-tablet.dtsi"
48 model = "Allwinner GT90H Dual Core Tablet (v4)";
49 compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23";
59 firmware-name = "gsl3675-gt90h.fw";
60 touchscreen-size-x = <1792>;
61 touchscreen-size-y = <1024>;
[all …]
H A Dsun8i-a33-ga10h-v1.1.dts4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun8i-a33.dtsi"
45 #include "sun8i-reference-design-tablet.dtsi"
48 model = "Allwinner GA10H Quad Core Tablet (v1.1)";
49 compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33";
52 /* Make u-boot set mac-address for rtl8703as (no eeprom) */
64 firmware-name = "gsl3675-ga10h.fw";
65 touchscreen-size-x = <1630>;
[all …]
H A Dsun6i-a31s-sina31s.dts2 * Copyright 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /* The SinA31s development board has the SinA31s core board soldered on */
44 #include "sun6i-a31s-sina31s-core.dtsi"
46 #include <dt-bindings/input/input.h>
50 compatible = "sinlinx,sina31s-sdk", "allwinner,sun6i-a31s";
53 stdout-path = "serial0:115200n8";
56 hdmi-connector {
57 compatible = "hdmi-connector";
[all …]
H A Dsun4i-a10-itead-iteaduino-plus.dts3 * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
44 /dts-v1/;
45 #include "sun4i-a10.dtsi"
46 #include "sunxi-itead-core-common.dtsi"
50 compatible = "itead,iteaduino-plus-a10", "allwinner,sun4i-a10";
54 target-supply = <&reg_ahci_5v>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&emac_pins>;
[all …]
H A Dsun7i-a20-itead-ibox.dts2 * Copyright 2015 - Marcus Cooper <codekipper@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
43 /dts-v1/;
44 #include "sun7i-a20.dtsi"
45 #include "sunxi-itead-core-common.dtsi"
49 compatible = "itead,itead-ibox-a20", "allwinner,sun7i-a20";
52 compatible = "gpio-leds";
53 pinctrl-names = "default";
54 pinctrl-0 = <&led_pins_itead_core>;
[all …]
H A Dsun50i-a64-sopine.dtsi4 * Based on sun50i-a64-pine64.dts, which is:
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
46 #include "sun50i-a64.dtsi"
48 #include <dt-bindings/gpio/gpio.h>
51 pinctrl-names = "default";
52 pinctrl-0 = <&mmc0_pins>;
53 vmmc-supply = <&reg_dcdc1>;
54 non-removable;
55 disable-wp;
[all …]
/openbmc/u-boot/board/theobroma-systems/puma_rk3399/
H A DREADME4 The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
5 RK3399 in a Qseven-compatible form-factor.
7 RK3399-Q7 features:
8 * CPU: ARMv8 64bit Big-Little architecture,
9 * Big: dual-core Cortex-A72
10 * Little: quad-core Cortex-A53
12 * DRAM: 4GB-128MB dual-channel
17 * USB3.0 dual role port
22 * Companion Controller: onboard additional Cortex-M0 microcontroller
27 Here is the step-by-step to boot to U-Boot on rk3399.
[all …]
/openbmc/u-boot/arch/arm/mach-mediatek/
H A DKconfig17 The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
18 including NEON and GPU, Mali-450 graphics, several DDR3 options,
19 crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
30 The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7
31 including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-support/rdma-core/
H A Drdma-core_51.0.bb8 SRC_URI = "git://github.com/linux-rdma/rdma-core.git;branch=master;protocol=https \
9 file://0001-cmake-Allow-SYSTEMCTL_BIN-to-be-overridden-from-envi.patch \
10 file://0001-include-libgen.h-for-basename.patch \
11 file://0001-librdmacm-Use-overloadable-function-attribute-with-c.patch \
16 #Default Dual License https://github.com/linux-rdma/rdma-core/blob/master/COPYING.md
17 LICENSE = "BSD-2-Clause | GPL-2.0-only"
22 -DCMAKE_INSTALL_SYSTEMD_SERVICEDIR=${systemd_system_unitdir} \
23 -DSYSTEMCTL_BIN=${base_bindir}/systemctl \
24 -DCMAKE_INSTALL_PERLDIR=${libdir}/perl5/${@get_perl_version(d)} \
25 -DNO_MAN_PAGES=1 \
[all …]
/openbmc/u-boot/board/google/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
15 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
20 and it provides a 2560x1700 high resolution touch-enabled LCD
24 bool "Chromebook link 64-bit"
27 U-Boot is built as a 64-bit binary. This allows testing while this
37 Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
47 Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
53 resolution touch-enabled LCD display.
/openbmc/u-boot/arch/arm/mach-imx/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
18 #include <asm/mach-imx/boot_mode.h>
28 static u32 reset_cause = -1;
34 if (reset_cause == -1) { in get_imx_reset_cause()
35 reset_cause = readl(&src_regs->srsr); in get_imx_reset_cause()
36 /* preserve the value for U-Boot proper */ in get_imx_reset_cause()
38 writel(reset_cause, &src_regs->srsr); in get_imx_reset_cause()
63 return "JTAG HIGH-Z"; in get_reset_cause()
117 * imx_ddr_size - return size in bytes of DRAM according MMDC config
[all …]
/openbmc/u-boot/drivers/spi/
H A DKconfig16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
33 IP core. Please find details on the "Embedded Peripherals IP
56 this Andestech IP core.
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
81 SPI core.
94 Enable the Broadcom set-top box SPI driver. This driver can
96 Broadcom SPI core.
101 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
103 Cadence IP core.
[all …]
/openbmc/u-boot/board/rockchip/evb_rk3399/
H A DREADME4 RK3399 key features we might use in U-Boot:
5 * CPU: ARMv8 64bit Big-Little architecture,
6 * Big: dual-core Cortex-A72
7 * Little: quad-core Cortex-A53
9 * DRAM: 4GB-128MB dual-channel
12 * USB: USB3.0 typc-C port *2 with dwc3 controller
25 * load and verify U-Boot image
27 Here is the step-by-step to boot to U-Boot on rk3399.
34 > git clone https://github.com/ARM-software/arm-trusted-firmware.git
35 > git clone https://github.com/rockchip-linux/rkbin.git
[all …]
/openbmc/qemu/docs/system/devices/
H A Dcan.rst22 open-source/design/hardware solution. The core designer
34 ----------------------------------------------------------
38 (1) CAN bus Kvaser PCI CAN-S (single SJA1000 channel) board. QEMU startup options::
40 -object can-bus,id=canbus0
41 -device kvaser_pci,canbus=canbus0
43 Add "can-host-socketcan" object to connect device to host system CAN bus::
45 -object can-host-socketcan,id=canhost0,if=can0,canbus=canbus0
47 (2) CAN bus PCM-3680I PCI (dual SJA1000 channel) emulation::
49 -object can-bus,id=canbus0
50 -device pcm3680_pci,canbus0=canbus0,canbus1=canbus0
[all …]
/openbmc/qemu/docs/system/arm/
H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
16 - OCM 256KB
[all …]
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
4 It combines Power Architecture e500v2 and DSP StarCore SC3850 core
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
[all …]
/openbmc/docs/designs/mctp/
H A Dmctp-userspace.md14 The MCTP core specification just provides the packetisation, routing and
20 provides a socket-based interface for other processes to send and receive
24 handling local MCTP-stack configuration, like local EID assignments.
28 1. the core MCTP stack
30 2. one or more binding implementations (eg, MCTP-over-serial), which interact
33 3. an interface to handler applications over a unix-domain socket.
38 - an "upper" messaging transmit/receive interface, for tx/rx of a full message
41 - a "lower" hardware binding for transmit/receive of individual packets,
42 providing a method for the core to tx/rx each packet to hardware, and defines
45 The lower interface would be plugged in to one of a number of hardware-specific
[all …]

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