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Searched full:ddr2 (Results 1 – 25 of 166) sorted by relevance

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/openbmc/u-boot/board/laird/wb45n/
H A Dwb45n.c146 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
148 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); in ddr2_conf()
150 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
156 ddr2->rtr = 0x411; in ddr2_conf()
158 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
167 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
172 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
182 struct atmel_mpddrc_config ddr2; in mem_init() local
185 ddr2_conf(&ddr2); in mem_init()
187 /* enable DDR2 clock */ in mem_init()
[all …]
/openbmc/u-boot/board/atmel/at91sam9x5ek/
H A Dat91sam9x5ek.c152 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
154 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
156 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
162 ddr2->rtr = 0x411; in ddr2_conf()
164 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
173 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
178 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
189 struct atmel_mpddrc_config ddr2; in mem_init() local
192 ddr2_conf(&ddr2); in mem_init()
194 /* enable DDR2 clock */ in mem_init()
[all …]
/openbmc/u-boot/board/atmel/sama5d3_xplained/
H A Dsama5d3_xplained.c133 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
135 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
137 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
146 * As the DDR2-SDRAm device requires a refresh time is 7.8125us in ddr2_conf()
149 ddr2->rtr = 0x411; in ddr2_conf()
151 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
160 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
165 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
174 struct atmel_mpddrc_config ddr2; in mem_init() local
176 ddr2_conf(&ddr2); in mem_init()
[all …]
/openbmc/u-boot/board/laird/wb50n/
H A Dwb50n.c139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM); in ddr2_conf()
143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | in ddr2_conf()
150 ddr2->rtr = 0x411; in ddr2_conf()
152 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
161 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
166 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
176 struct atmel_mpddrc_config ddr2; in mem_init() local
178 ddr2_conf(&ddr2); in mem_init()
188 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
/openbmc/u-boot/board/atmel/sama5d4ek/
H A Dsama5d4ek.c139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
150 ddr2->rtr = 0x2b0; in ddr2_conf()
152 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
161 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
166 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
175 struct atmel_mpddrc_config ddr2; in mem_init() local
179 ddr2_conf(&ddr2); in mem_init()
199 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
/openbmc/u-boot/board/atmel/sama5d4_xplained/
H A Dsama5d4_xplained.c153 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
155 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
157 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
165 ddr2->rtr = 0x2b0; in ddr2_conf()
167 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
176 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
181 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
190 struct atmel_mpddrc_config ddr2; in mem_init() local
192 ddr2_conf(&ddr2); in mem_init()
199 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); in mem_init()
/openbmc/u-boot/board/atmel/at91sam9n12ek/
H A Dat91sam9n12ek.c236 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
238 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
240 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
246 ddr2->rtr = 0x411; in ddr2_conf()
248 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
257 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
262 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
272 struct atmel_mpddrc_config ddr2; in mem_init() local
275 ddr2_conf(&ddr2); in mem_init()
277 /* enable DDR2 clock */ in mem_init()
[all …]
/openbmc/u-boot/board/atmel/sama5d3xek/
H A Dsama5d3xek.c207 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
209 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
211 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
220 * As the DDR2-SDRAm device requires a refresh time is 7.8125us in ddr2_conf()
223 ddr2->rtr = 0x411; in ddr2_conf()
225 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | in ddr2_conf()
234 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | in ddr2_conf()
239 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | in ddr2_conf()
248 struct atmel_mpddrc_config ddr2; in mem_init() local
250 ddr2_conf(&ddr2); in mem_init()
[all …]
/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Dsama5d2_devices.c55 return "SAMA5D225 128M bits DDR2 SDRAM"; in get_cpu_name()
57 return "SAMA5D27 512M bits DDR2 SDRAM"; in get_cpu_name()
59 return "SAMA5D27 1G bits DDR2 SDRAM"; in get_cpu_name()
61 return "SAMA5D28 1G bits DDR2 SDRAM"; in get_cpu_name()
/openbmc/u-boot/board/mini-box/picosam9g45/
H A Dpicosam9g45.c49 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
51 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
53 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
58 ddr2->rtr = 0x24b; in ddr2_conf()
60 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
69 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
74 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
83 struct atmel_mpddrc_config ddr2; in mem_init() local
86 ddr2_conf(&ddr2); in mem_init()
90 /* Chip select 1 is for DDR2/SDRAM */ in mem_init()
[all …]
/openbmc/u-boot/board/siemens/corvus/
H A Dboard.c136 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
138 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
140 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
145 ddr2->rtr = 0x24b; in ddr2_conf()
147 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
156 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
161 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
169 struct atmel_mpddrc_config ddr2; in mem_init() local
171 ddr2_conf(&ddr2); in mem_init()
176 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
/openbmc/u-boot/board/atmel/at91sam9m10g45ek/
H A Dat91sam9m10g45ek.c94 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) in ddr2_conf() argument
96 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
98 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | in ddr2_conf()
103 ddr2->rtr = 0x24b; in ddr2_conf()
105 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ in ddr2_conf()
114 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ in ddr2_conf()
119 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | in ddr2_conf()
127 struct atmel_mpddrc_config ddr2; in mem_init() local
129 ddr2_conf(&ddr2); in mem_init()
134 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); in mem_init()
/openbmc/u-boot/board/xes/xpedite517x/
H A Dddr.c37 * Usually only needed with heavy load/very high speed (>DDR2-800)
55 /* DDR2 600/667 */
63 /* DDR2 800 */
74 /* DDR2 600/667 */
82 /* DDR2 800 */
/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c38 * Usually only needed with heavy load/very high speed (>DDR2-800)
40 * ====== XPedite5370 DDR2-600 read delay calculations ======
83 * ====== XPedite5370 DDR2-800 read delay calculations ======
143 * period at DDR2-600 or DDR2-800, so no additional delay is needed over
165 /* DDR2 600/667 */
173 /* DDR2 800 */
184 /* DDR2 600/667 */
192 /* DDR2 800 */
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5d4.h178 #define H64MX_SLAVE_DDRC_PORT0 3 /* DDR2 Port0-AESOTF */
179 #define H64MX_SLAVE_DDRC_PORT1 4 /* DDR2 Port1 */
180 #define H64MX_SLAVE_DDRC_PORT2 5 /* DDR2 Port2 */
181 #define H64MX_SLAVE_DDRC_PORT3 6 /* DDR2 Port3 */
182 #define H64MX_SLAVE_DDRC_PORT4 7 /* DDR2 Port4 */
183 #define H64MX_SLAVE_DDRC_PORT5 8 /* DDR2 Port5 */
184 #define H64MX_SLAVE_DDRC_PORT6 9 /* DDR2 Port6 */
185 #define H64MX_SLAVE_DDRC_PORT7 10 /* DDR2 Port7 */
H A Dsama5d2.h182 #define H64MX_SLAVE_DDRC_PORT0 2 /* DDR2 Port0-AESOTF */
183 #define H64MX_SLAVE_DDRC_PORT1 3 /* DDR2 Port1 */
184 #define H64MX_SLAVE_DDRC_PORT2 4 /* DDR2 Port2 */
185 #define H64MX_SLAVE_DDRC_PORT3 5 /* DDR2 Port3 */
186 #define H64MX_SLAVE_DDRC_PORT4 6 /* DDR2 Port4 */
187 #define H64MX_SLAVE_DDRC_PORT5 7 /* DDR2 Port5 */
188 #define H64MX_SLAVE_DDRC_PORT6 8 /* DDR2 Port6 */
189 #define H64MX_SLAVE_DDRC_PORT7 9 /* DDR2 Port7 */
/openbmc/u-boot/board/xes/xpedite520x/
H A Dddr.c17 * The SPD has an unspecified dimm type, but the DDR2 initialization in get_spd()
34 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
46 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig81 Enable Freescale DDR2 controller.
87 Enable Freescale DDR2 controller for MPC86xx SoCs.
137 bool "Freescale DDR2 controller"
/openbmc/u-boot/arch/mips/mach-mt7620/
H A DKconfig68 prompt "DDR2 size"
97 prompt "DDR2 chip width"
114 prompt "DDR2 bus width"
/openbmc/u-boot/board/freescale/mpc8548cds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/openbmc/u-boot/board/socrates/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8555cds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8541cds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
/openbmc/u-boot/board/sbc8641d/
H A Dddr.c19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()

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