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Searched full:ctl1 (Results 1 – 25 of 39) sorted by relevance

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/openbmc/linux/drivers/mtd/nand/raw/
H A Dcafe_nand.c65 uint32_t ctl1; member
166 uint32_t ctl1; in cafe_nand_cmdfunc() local
175 ctl1 = cafe->ctl1; in cafe_nand_cmdfunc()
177 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", in cafe_nand_cmdfunc()
178 cafe->ctl1, cafe->nr_data); in cafe_nand_cmdfunc()
212 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT); in cafe_nand_cmdfunc()
216 ctl1 |= (1<<26); /* rd */ in cafe_nand_cmdfunc()
223 ctl1 |= 1<<26; /* rd */ in cafe_nand_cmdfunc()
227 ctl1 |= 1<<25; /* wr */ in cafe_nand_cmdfunc()
231 ctl1 |= ((adrbytes-1)|8) << 27; in cafe_nand_cmdfunc()
[all …]
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_smbus-test.c108 /* CTL1 fields */
215 uint8_t ctl1; in start_transfer() local
217 ctl1 = CTL1_START | CTL1_INTEN | CTL1_STASTRE; in start_transfer()
218 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in start_transfer()
228 uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in stop_transfer() local
230 ctl1 &= ~(CTL1_START | CTL1_ACK); in stop_transfer()
231 ctl1 |= CTL1_STOP | CTL1_INTEN | CTL1_EOBINTE; in stop_transfer()
232 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in stop_transfer()
233 ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in stop_transfer()
234 g_assert_false(ctl1 & CTL1_STOP); in stop_transfer()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Ddvo_tfp410.c240 u8 ctl1; in tfp410_dpms() local
242 if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1)) in tfp410_dpms()
246 ctl1 |= TFP410_CTL_1_PD; in tfp410_dpms()
248 ctl1 &= ~TFP410_CTL_1_PD; in tfp410_dpms()
250 tfp410_writeb(dvo, TFP410_CTL_1, ctl1); in tfp410_dpms()
255 u8 ctl1; in tfp410_get_hw_state() local
257 if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1)) in tfp410_get_hw_state()
260 if (ctl1 & TFP410_CTL_1_PD) in tfp410_get_hw_state()
H A Dintel_backlight_regs.h79 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
/openbmc/linux/drivers/rtc/
H A Drtc-rzn1.c171 u32 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); in rzn1_rtc_alarm_irq_enable() local
174 ctl1 |= RZN1_RTC_CTL1_ALME; in rzn1_rtc_alarm_irq_enable()
176 ctl1 &= ~RZN1_RTC_CTL1_ALME; in rzn1_rtc_alarm_irq_enable()
178 writel(ctl1, rtc->base + RZN1_RTC_CTL1); in rzn1_rtc_alarm_irq_enable()
189 u32 ctl1; in rzn1_rtc_read_alarm() local
211 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); in rzn1_rtc_read_alarm()
212 alrm->enabled = !!(ctl1 & RZN1_RTC_CTL1_ALME); in rzn1_rtc_read_alarm()
/openbmc/linux/arch/arm/mach-sa1100/
H A Dneponset.c89 GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
90 GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
91 GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
101 GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
102 GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
103 GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
329 neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1", in neponset_probe()
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c215 u32 ctl1, ctl6; in ar9002_set_txdesc() local
226 ctl1 = i->buf_len[0] | (i->is_last ? 0 : AR_TxMore); in ar9002_set_txdesc()
256 WRITE_ONCE(ads->ds_ctl1, ctl1); in ar9002_set_txdesc()
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
272 ctl1 |= AR_IsAggr | AR_MoreAggr; in ar9002_set_txdesc()
276 ctl1 |= AR_IsAggr; in ar9002_set_txdesc()
292 WRITE_ONCE(ads->ds_ctl1, ctl1); in ar9002_set_txdesc()
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.c116 u32 ctl1; in bgmac_dma_tx_add_buf() local
121 ctl1 = len & BGMAC_DESC_CTL1_LEN; in bgmac_dma_tx_add_buf()
128 dma_desc->ctl1 = cpu_to_le32(ctl1); in bgmac_dma_tx_add_buf()
217 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); in bgmac_dma_tx_add() local
218 int len = ctl1 & BGMAC_DESC_CTL1_LEN; in bgmac_dma_tx_add()
251 u32 ctl0, ctl1; in bgmac_dma_tx_free() local
258 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); in bgmac_dma_tx_free()
259 len = ctl1 & BGMAC_DESC_CTL1_LEN; in bgmac_dma_tx_free()
381 u32 ctl0 = 0, ctl1 = 0; in bgmac_dma_rx_setup_desc() local
385 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; in bgmac_dma_rx_setup_desc()
[all …]
/openbmc/qemu/hw/i2c/
H A Dnpcm7xx_smbus.c105 /* CTL1 fields */
204 if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { in npcm7xx_smbus_update_irq()
205 level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && in npcm7xx_smbus_update_irq()
210 (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && in npcm7xx_smbus_update_irq()
212 (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && in npcm7xx_smbus_update_irq()
401 if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { in npcm7xx_smbus_send_address()
555 s->ctl1 = KEEP_OLD_BIT(s->ctl1, value, in npcm7xx_smbus_write_ctl1()
575 s->ctl1 = 0; in npcm7xx_smbus_write_ctl2()
677 value = s->ctl1; in npcm7xx_smbus_read()
999 s->ctl1 = NPCM7XX_SMB_CTL1_INIT_VAL; in npcm7xx_smbus_enter_reset()
[all …]
/openbmc/linux/drivers/net/can/mscan/
H A Dmscan.c627 u8 ctl1; in register_mscandev() local
629 ctl1 = in_8(&regs->canctl1); in register_mscandev()
631 ctl1 |= MSCAN_CLKSRC; in register_mscandev()
633 ctl1 &= ~MSCAN_CLKSRC; in register_mscandev()
637 ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */ in register_mscandev()
640 ctl1 |= MSCAN_CANE; in register_mscandev()
641 out_8(&regs->canctl1, ctl1); in register_mscandev()
/openbmc/qemu/include/hw/i2c/
H A Dnpcm7xx_smbus.h51 * @ctl1: The control register 1.
84 uint8_t ctl1; member
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dxhci-keystone.h15 unsigned int phy_pipe; /* ctl1 */
/openbmc/linux/drivers/pci/pcie/
H A Daspm.c444 u32 ctl1 = 0, ctl2 = 0; in aspm_calc_l12_info() local
480 ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; in aspm_calc_l12_info()
488 if (ctl1 == pctl1 && ctl1 == cctl1 && in aspm_calc_l12_info()
509 PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1); in aspm_calc_l12_info()
514 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); in aspm_calc_l12_info()
517 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1); in aspm_calc_l12_info()
/openbmc/u-boot/board/freescale/mx51evk/
H A Dimximage.cfg102 /* Write to CTL1 */
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dlvds.yaml78 CTL1: VSync
/openbmc/linux/drivers/phy/amlogic/
H A Dphy-meson8-hdmi-tx.c21 * HHI_HDMI_PHY_CNTL0 register. CTL0 and CTL1 is all we know about.
/openbmc/linux/sound/soc/codecs/
H A Dcs35l33.h24 #define CS35L33_BST_CTL1 0x0B /* Boost Converter CTL1 */
H A Dcs35l35.h27 #define CS35L35_SP_FMT_CTL1 0x0D /* Serial Port Format CTL1 */
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_ctl.c740 * In bonded DSI case, CTL0 and CTL1 are always assigned to two DSI in mdp5_ctlm_init()
741 * interfaces to support single FLUSH feature (Flush CTL0 and CTL1 when in mdp5_ctlm_init()
/openbmc/linux/sound/mips/
H A Dhal2.h132 /* Bits in CTL1 register */
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Ddma.c184 u32 ctl0 = 0, ctl1 = 0; in op64_fill_descriptor() local
203 ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT; in op64_fill_descriptor()
204 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) in op64_fill_descriptor()
208 desc->dma64.control1 = cpu_to_le32(ctl1); in op64_fill_descriptor()
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-cframe-reg.h76 REG32(CTL1, 0x84)
/openbmc/u-boot/drivers/video/
H A Di915_reg.h113 * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
/openbmc/linux/drivers/dma/
H A Dpch_dma.c745 pd->regs.dma_ctl1 = dma_readl(pd, CTL1); in pch_dma_save_regs()
768 dma_writel(pd, CTL1, pd->regs.dma_ctl1); in pch_dma_restore_regs()
/openbmc/linux/drivers/iio/adc/
H A Dtwl4030-madc.c800 dev_err(&pdev->dev, "unable to read reg BCI CTL1 0x%X\n", in twl4030_madc_probe()
808 dev_err(&pdev->dev, "unable to write reg BCI Ctl1 0x%X\n", in twl4030_madc_probe()

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