1*ea8a12e3SMaxime Ripard# SPDX-License-Identifier: GPL-2.0 2*ea8a12e3SMaxime Ripard%YAML 1.2 3*ea8a12e3SMaxime Ripard--- 4*ea8a12e3SMaxime Ripard$id: http://devicetree.org/schemas/display/lvds.yaml# 5*ea8a12e3SMaxime Ripard$schema: http://devicetree.org/meta-schemas/core.yaml# 6*ea8a12e3SMaxime Ripard 7*ea8a12e3SMaxime Ripardtitle: LVDS Display Common Properties 8*ea8a12e3SMaxime Ripard 9*ea8a12e3SMaxime Ripardmaintainers: 10*ea8a12e3SMaxime Ripard - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*ea8a12e3SMaxime Ripard - Thierry Reding <thierry.reding@gmail.com> 12*ea8a12e3SMaxime Ripard 13*ea8a12e3SMaxime Riparddescription: |+ 14*ea8a12e3SMaxime Ripard LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 15*ea8a12e3SMaxime Ripard incompatible data link layers have been used over time to transmit image data 16*ea8a12e3SMaxime Ripard to LVDS devices. This bindings supports devices compatible with the following 17*ea8a12e3SMaxime Ripard specifications. 18*ea8a12e3SMaxime Ripard 19*ea8a12e3SMaxime Ripard [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 20*ea8a12e3SMaxime Ripard 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 21*ea8a12e3SMaxime Ripard [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 22*ea8a12e3SMaxime Ripard Semiconductor 23*ea8a12e3SMaxime Ripard [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 24*ea8a12e3SMaxime Ripard Electronics Standards Association (VESA) 25*ea8a12e3SMaxime Ripard 26*ea8a12e3SMaxime Ripard Device compatible with those specifications have been marketed under the 27*ea8a12e3SMaxime Ripard FPD-Link and FlatLink brands. 28*ea8a12e3SMaxime Ripard 29*ea8a12e3SMaxime Ripardproperties: 30*ea8a12e3SMaxime Ripard data-mapping: 31*ea8a12e3SMaxime Ripard enum: 32*ea8a12e3SMaxime Ripard - jeida-18 33*ea8a12e3SMaxime Ripard - jeida-24 34*ea8a12e3SMaxime Ripard - vesa-24 35*ea8a12e3SMaxime Ripard description: | 36*ea8a12e3SMaxime Ripard The color signals mapping order. 37*ea8a12e3SMaxime Ripard 38*ea8a12e3SMaxime Ripard LVDS data mappings are defined as follows. 39*ea8a12e3SMaxime Ripard 40*ea8a12e3SMaxime Ripard - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 41*ea8a12e3SMaxime Ripard [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 42*ea8a12e3SMaxime Ripard 43*ea8a12e3SMaxime Ripard Slot 0 1 2 3 4 5 6 44*ea8a12e3SMaxime Ripard ________________ _________________ 45*ea8a12e3SMaxime Ripard Clock \_______________________/ 46*ea8a12e3SMaxime Ripard ______ ______ ______ ______ ______ ______ ______ 47*ea8a12e3SMaxime Ripard DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 48*ea8a12e3SMaxime Ripard DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 49*ea8a12e3SMaxime Ripard DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 50*ea8a12e3SMaxime Ripard 51*ea8a12e3SMaxime Ripard - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 52*ea8a12e3SMaxime Ripard specifications. Data are transferred as follows on 4 LVDS lanes. 53*ea8a12e3SMaxime Ripard 54*ea8a12e3SMaxime Ripard Slot 0 1 2 3 4 5 6 55*ea8a12e3SMaxime Ripard ________________ _________________ 56*ea8a12e3SMaxime Ripard Clock \_______________________/ 57*ea8a12e3SMaxime Ripard ______ ______ ______ ______ ______ ______ ______ 58*ea8a12e3SMaxime Ripard DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 59*ea8a12e3SMaxime Ripard DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 60*ea8a12e3SMaxime Ripard DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 61*ea8a12e3SMaxime Ripard DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 62*ea8a12e3SMaxime Ripard 63*ea8a12e3SMaxime Ripard - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 64*ea8a12e3SMaxime Ripard Data are transferred as follows on 4 LVDS lanes. 65*ea8a12e3SMaxime Ripard 66*ea8a12e3SMaxime Ripard Slot 0 1 2 3 4 5 6 67*ea8a12e3SMaxime Ripard ________________ _________________ 68*ea8a12e3SMaxime Ripard Clock \_______________________/ 69*ea8a12e3SMaxime Ripard ______ ______ ______ ______ ______ ______ ______ 70*ea8a12e3SMaxime Ripard DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 71*ea8a12e3SMaxime Ripard DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 72*ea8a12e3SMaxime Ripard DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 73*ea8a12e3SMaxime Ripard DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 74*ea8a12e3SMaxime Ripard 75*ea8a12e3SMaxime Ripard Control signals are mapped as follows. 76*ea8a12e3SMaxime Ripard 77*ea8a12e3SMaxime Ripard CTL0: HSync 78*ea8a12e3SMaxime Ripard CTL1: VSync 79*ea8a12e3SMaxime Ripard CTL2: Data Enable 80*ea8a12e3SMaxime Ripard CTL3: 0 81*ea8a12e3SMaxime Ripard 82*ea8a12e3SMaxime Ripard data-mirror: 83*ea8a12e3SMaxime Ripard type: boolean 84*ea8a12e3SMaxime Ripard description: 85*ea8a12e3SMaxime Ripard If set, reverse the bit order described in the data mappings below on all 86*ea8a12e3SMaxime Ripard data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6. 87*ea8a12e3SMaxime Ripard 88*ea8a12e3SMaxime RipardadditionalProperties: true 89*ea8a12e3SMaxime Ripard 90*ea8a12e3SMaxime Ripard... 91