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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
47 * - When we have CS1 populated we want to have it mapped after cs0 to allow
55 size = get_sdr_cs_size(CS0); in make_cs1_contiguous()
81 * - Get offset of cs from cs0 start
125 * - Code called once in C-Stack only context for CS0 and with early being
145 * from the first bank to the second. We will setup CS0, in do_sdrc_init()
170 write_sdrc_timings(CS0, sdrc_actim_base0, &timings); in do_sdrc_init()
180 * both CS0 and CS1 (such as some older versions of x-loader) in do_sdrc_init()
184 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), in do_sdrc_init()
185 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); in do_sdrc_init()
[all …]
H A Demif4.c41 if (cs == CS0) in get_sdr_cs_size()
49 * - Get offset of cs from cs0 start
131 size0 = get_sdr_cs_size(CS0); in dram_init()
135 * memory on CS0. in dram_init()
148 size0 = get_sdr_cs_size(CS0); in dram_init_banksize()
/openbmc/u-boot/drivers/ddr/fsl/
H A Doptions.c44 { /* cs0 */
71 { /* cs0 */
88 { /* cs0 */
100 { /* cs0 */
127 { /* cs0 */
148 { /* cs0 */
170 { /* cs0 */
187 { /* cs0 */
221 { /* cs0 */
247 { /* cs0 */
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-sx93246 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
18 By default, during the first phase, [PH0], CS0 is measured,
21 [PH1], CS1 is measured, CS0 and CS2 are shield:
23 [PH2], CS2 is measured, CS0 and CS1 are shield:
H A Dsysfs-class-watchdog110 chip at CS0 after booting from the alternate
114 from (CS0->CS1, CS1->CS0) to (CS0->CS0,
119 the SoC is in normal mapping state (i.e. booted from CS0),
/openbmc/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dsemtech,sx9310.yaml46 semtech,cs0-ground:
47 description: Indicates the CS0 sensor is connected to ground.
56 0 1 - CS0 + CS1
58 0 1 2 3 - CS0 + CS1 + CS2 + CS3
124 semtech,cs0-ground;
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-370-pinctrl.txt29 mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
45 mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
53 mpp32 32 gpio, spi0(cs0)
54 mpp33 33 gpio, dev(bootcs), spi0(cs0)
71 mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
86 mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
H A Dmarvell,armada-38x-pinctrl.txt36 mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0)
43 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
77 mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
H A Dmarvell,armada-39x-pinctrl.txt36 mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck)
44 mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
81 mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2)
H A Dmarvell,armada-375-pinctrl.txt24 mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
46 mpp30 30 gpio, ge1(txd0), spi1(cs0)
/openbmc/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-pxs2.c40 {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
41 {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
44 {BOOT_DEVICE_SPI, "SPI (4Byte CS0)"},
45 {BOOT_DEVICE_SPI, "SPI (3Byte CS0)"},
/openbmc/u-boot/board/ccv/xpress/
H A Dimximage.cfg160 DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
161 DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
162 DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
163 DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
165 device on CS0 */
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-n950-n9.dtsi359 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
365 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
372 * gpmc cs0 before gpmc_cs_program_settings:
373 * cs0 GPMC_CS_CONFIG1: 0xfd001202
374 * cs0 GPMC_CS_CONFIG2: 0x00181800
375 * cs0 GPMC_CS_CONFIG3: 0x00030300
376 * cs0 GPMC_CS_CONFIG4: 0x18001804
377 * cs0 GPMC_CS_CONFIG5: 0x03171d1d
378 * cs0 GPMC_CS_CONFIG6: 0x97080000
/openbmc/u-boot/board/sbc8548/
H A DREADME127 have U-Boot in the 8MB flash, tied to /CS0.
129 If you are running the default 8MB /CS0 settings but want to store an
141 Finally, if you are running the alternate 64MB /CS0 settings and want
176 JP12 CS0/CS6 swap see note[*] see note[*]
191 onto /CS0 and the SODIMM flash on /CS6 (default). When JP12
192 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
257 ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c206 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
373 ddr3_pbs_write_pup_dqs_reg(CS0, pup, INIT_WL_DELAY); in ddr3_pbs_tx()
452 ddr3_pbs_write_pup_dqs_reg(CS0, in ddr3_tx_shift_dqs_adll_step_before_fail()
505 ddr3_pbs_write_pup_dqs_reg(CS0, pup * (1 - ecc) + ECC_PUP * ecc, in ddr3_tx_shift_dqs_adll_step_before_fail()
646 [dq], CS0, in ddr3_pbs_rx()
654 DQ_NUM, CS0, in ddr3_pbs_rx()
701 (PUP_DQS_RD, CS0, in ddr3_pbs_rx()
717 [dq], CS0, in ddr3_pbs_rx()
748 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_pbs_rx()
886 ddr3_write_pup_reg(PUP_DQS_RD, CS0, PUP_BC, 0, INIT_RL_DELAY); in ddr3_pbs_rx()
[all …]
/openbmc/linux/drivers/staging/fbtft/
H A Dfb_agm1264k-fl.c32 #define CS0 gpio.aux[0] macro
101 if (!par->CS0) { in verify_gpios()
103 "Missing info about 'cs0' gpio. Aborting.\n"); in verify_gpios()
130 } else if (strcasecmp(gpio->name, "cs0") == 0) { in request_gpios_match()
132 par->CS0 = gpio->gpio; in request_gpios_match()
184 gpiod_set_value(par->CS0, 0); in write_reg8_bus8()
187 /* cs0 */ in write_reg8_bus8()
188 gpiod_set_value(par->CS0, 1); in write_reg8_bus8()
387 gpiod_set_value(par->CS0, 0); in write_vmem()
/openbmc/u-boot/board/freescale/mpc837xemds/
H A DREADME34 J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
55 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
/openbmc/phosphor-bmc-code-mgmt/static/
H A Dobmc-flash-bmc-alt@.service.in2 Description=Flash image-bmc to the alt chip and reset cs0
14 ExecStartPost=-/usr/bin/reset-cs0-aspeed
/openbmc/linux/drivers/watchdog/
H A Daspeed_wdt.c216 /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
249 * ast2400: a way to get access to the primary SPI flash chip at CS0
252 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
256 * mapping state (i.e. booted from CS0), clearing those bits does nothing for
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h47 #define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */
54 #define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */
59 #define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */
/openbmc/qemu/tests/qtest/
H A Daspeed_smc-test.c47 /* fmc cs0 with n25q256a flash */ in test_palmetto_bmc()
94 /* fmc cs0 with mx25l25635e flash */ in test_ast2500_evb()
137 /* fmc cs0 with mx66u51235f flash */ in test_ast2600_evb()
180 /* fmc cs0 with w25q80bl flash */ in test_ast1030_evb()
/openbmc/linux/arch/hexagon/kernel/
H A Dptrace.c64 membuf_store(&to, regs->cs0); in genregs_get()
112 INEXT(&regs->cs0, cs0); in genregs_set()
H A Dsignal.c54 err |= __put_user(regs->cs0, &sc->sc_regs.cs0); in setup_sigcontext()
84 err |= __get_user(regs->cs0, &sc->sc_regs.cs0); in restore_sigcontext()
/openbmc/u-boot/doc/
H A DREADME.fsl-ddr31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
37 | |CS0 Only| | | {CS0+CS1} | |
40 | |CS0 Only| | | {CS0+CS1} | |
43 | |CS0 Only| | | {CS0+CS1} | |
46 | | | | | {CS0+CS1} | |
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
94 # bank(chip-select) interleaving cs0+cs1
100 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
103 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
[all …]
/openbmc/u-boot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg123 # bit3-2: 00, CS0 hit selected
132 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
133 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0

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