| /openbmc/linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_ttm.h | 1 /* SPDX-License-Identifier: MIT */
13 * i915_gem_to_ttm - Convert a struct drm_i915_gem_object to a
22 return &obj->__do_not_access; in i915_gem_to_ttm()
31 * i915_ttm_is_ghost_object - Check if the ttm bo is a ghost object.
39 return bo->destroy != i915_ttm_bo_destroy; in i915_ttm_is_ghost_object()
43 * i915_ttm_to_gem - Convert a struct ttm_buffer_object to an embedding
82 * i915_ttm_gtt_binds_lmem - Should the memory be viewed as LMEM by the GTT?
85 * Return: true if memory should be viewed as LMEM for GTT binding purposes,
90 return mem->mem_type != I915_PL_SYSTEM; in i915_ttm_gtt_binds_lmem()
94 * i915_ttm_cpu_maps_iomem - Should the memory be viewed as IOMEM by the CPU?
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| /openbmc/linux/Documentation/RCU/ |
| H A D | RTFP.txt | 4 This document describes RCU-related publications, and is followed by
19 with short-lived threads, such as the K42 research operating system.
20 However, Linux has long-lived tasks, so more is needed.
23 serialization, which is an RCU-like mechanism that relies on the presence
27 that these overheads were not so expensive in the mid-80s. Nonetheless,
28 passive serialization appears to be the first deferred-destruction
30 has lapsed, so this approach may be used in non-GPL software, if desired.
34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].
36 this paper helped inspire the update-side batching used in the later
38 a description of Argus that noted that use of out-of-date values can
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| /openbmc/qemu/docs/system/ |
| H A D | target-sparc.rst | 1 .. _Sparc32-System-emulator:
4 -----------------------
6 Use the executable ``qemu-system-sparc`` to simulate the following Sun4m
9 - SPARCstation 4
11 - SPARCstation 5
13 - SPARCstation 10
15 - SPARCstation 20
17 - SPARCserver 600MP
19 - SPARCstation LX
21 - SPARCstation Voyager
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| /openbmc/linux/tools/perf/Documentation/ |
| H A D | perf-timechart.txt | 1 perf-timechart(1)
5 ----
6 perf-timechart - Tool to visualize total system behavior during a workload
9 --------
14 -----------
19 and CPU events (task switches, running times, CPU power states, etc),
20 but it's possible to record IO (disk, network) activity using -I argument.
23 that can be viewed with popular SVG viewers such as 'Inkscape'. Depending
24 on the events in the perf.data file, timechart will contain scheduler/cpu
34 -----------------
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|
| H A D | perf-arm-spe.txt | 1 perf-arm-spe(1)
5 ----
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
9 --------
11 'perf record' -e arm_spe//
14 -----------
17 events down to individual instructions. Rather than being interrupt-driven, it picks an
33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The
35 sample. This minimum interval is used by the driver if no interval is specified. A pseudo-random
62 ----------------
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | socionext,uniphier-system-bus.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
30 "#address-cells":
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| /openbmc/linux/Documentation/mm/ |
| H A D | numa.rst | 17 Each of the 'cells' may be viewed as an SMP [symmetric multi-processor] subset
18 of the system--although some components necessary for a stand-alone SMP system
20 connected together with some sort of system interconnect--e.g., a crossbar or
21 point-to-point link are common types of NUMA system interconnects. Both of
27 to and accessible from any CPU attached to any cell and cache coherency
31 away the cell containing the CPU or IO bus making the memory access is from the
41 [cache misses] to be to "local" memory--memory on the same cell, if any--or
51 "closer" nodes--nodes that map to closer cells--will generally experience
63 the existing nodes--or the system memory for non-NUMA platforms--into multiple
66 application features on non-NUMA platforms, and as a sort of memory resource
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|
| /openbmc/qemu/docs/devel/ |
| H A D | tcg.rst | 9 are very complicated and highly CPU dependent. QEMU uses some tricks
14 Generator". For more information, please take a look at :ref:`tcg-ops-ref`.
19 CPU state optimisations
20 -----------------------
25 CPU cannot change in it. The state is recorded in the Translation
29 to other aspects of the CPU state. For example, on x86, if the SS,
34 ---------------------
37 Program Counter (PC) and other CPU state information (such as the CS
48 callback to be re-evaluated before executing additional instructions.
49 It is mandatory to exit this way after any CPU state changes that may
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3328-a1.dts | 1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 // Copyright (c) 2017-2019 Arm Ltd.
4 /dts-v1/;
9 compatible = "azw,beelink-a1", "rockchip,rk3328";
17 * UART pins, as viewed with bottom of case removed:
20 * /-------
21 * L / o <- Gnd
22 * e / o <-- Rx
23 * f / o <--- Tx
24 * t / o <---- +3.3v
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| /openbmc/linux/Documentation/virt/hyperv/ |
| H A D | vmbus.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 VMbus is a software construct provided by Hyper-V to guest VMs. It
7 devices that Hyper-V presents to guest VMs. The control path is
11 and the synthetic device implementation that is part of Hyper-V, and
12 signaling primitives to allow Hyper-V and the guest to interrupt
17 establishes the VMbus control path with the Hyper-V host, then
21 Most synthetic devices offered by Hyper-V have a corresponding Linux
29 * PCI device pass-thru
34 * Key/Value Pair (KVP) exchange with Hyper-V
35 * Hyper-V online backup (a.k.a. VSS)
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|
| /openbmc/linux/lib/ |
| H A D | percpu-refcount.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/percpu-refcount.h>
13 * don't try to detect the ref hitting 0 - which means that get/put can just
15 * particular cpu can (and will) wrap - this is fine, when we go to shutdown the
24 * the ref hitting 0 on every put - this would require global synchronization
37 #define PERCPU_COUNT_BIAS (1LU << (BITS_PER_LONG - 1))
45 (ref->percpu_count_ptr & ~__PERCPU_REF_ATOMIC_DEAD); in percpu_count_ptr()
49 * percpu_ref_init - initialize a percpu refcount
60 * Note that @release must not sleep - it may potentially be called from RCU
71 ref->percpu_count_ptr = (unsigned long) in percpu_ref_init()
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| /openbmc/linux/Documentation/admin-guide/mm/ |
| H A D | numa_memory_policy.rst | 10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
98 mapping-- i.e., at Copy-On-Write.
101 virtual address space--a.k.a. threads--independent of when
106 are NOT inheritable across exec(). Thus, only NUMA-aware
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|
| /openbmc/linux/Documentation/trace/coresight/ |
| H A D | coresight-config.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
30 --------
41 accesses in the driver - the resource usage and parameter descriptions
67 system - which is described below.
74 --------------
82 enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a
118 perf record -e cs_etm/autofdo/ myapp
137 system can be viewed using the configfs API.
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|
| /openbmc/linux/Documentation/ |
| H A D | memory-barriers.txt | 19 documentation at tools/memory-model/. Nevertheless, even this memory
20 model should be viewed as the collective opinion of its maintainers rather
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
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|
| /openbmc/linux/arch/arm/probes/ |
| H A D | decode.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
32 /* We need a run-time check to determine str_pc_offset */
41 long cpsr = regs->ARM_cpsr; in bx_write_pc()
49 regs->ARM_cpsr = cpsr; in bx_write_pc()
50 regs->ARM_pc = pcv; in bx_write_pc()
62 /* We need run-time testing to determine if load_write_pc() should interwork. */
73 regs->ARM_pc = pcv; in load_write_pc()
90 /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
101 regs->ARM_pc = pcv; in alu_write_pc()
118 * viewed as an array of these and declared like:
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|
| /openbmc/linux/Documentation/networking/dsa/ |
| H A D | dsa.rst | 22 An Ethernet switch typically comprises multiple front-panel ports and one
23 or more CPU or management ports. The DSA subsystem currently relies on the
27 gateways, or even top-of-rack switches. This host Ethernet controller will
28 be later referred to as "master" and "cpu" in DSA terminology and code.
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
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|
| /openbmc/linux/drivers/media/pci/cx18/ |
| H A D | cx23418.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <media/drv-intf/cx2341x.h>
19 IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
21 OUT[0] - Task handle. This handle is passed along with commands to
23 ReturnCode - One of the ERR_SYS_... */
27 IN[0] - Task handle. Hanlde of the task to destroy
28 ReturnCode - One of the ERR_SYS_... */
31 /* All commands for CPU have the following mask set */
49 IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?)
50 IN[1] - caller buffer address, or 0
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|
| /openbmc/linux/Documentation/networking/device_drivers/ethernet/aquantia/ |
| H A D | atlantic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 For the aQuantia Multi-Gigabit PCI Express Family of Ethernet Adapters
12 - Identifying Your Adapter
13 - Configuration
14 - Supported ethtool options
15 - Command Line Parameters
16 - Config file parameters
17 - Support
18 - License
23 The driver in this release is compatible with AQC-100, AQC-107, AQC-108
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|
| /openbmc/u-boot/drivers/dma/ |
| H A D | apbh_dma.c | 1 // SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
22 #include <asm/mach-imx/regs-apbh.h>
34 return -EINVAL; in mxs_dma_validate_chan()
37 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) in mxs_dma_validate_chan()
38 return -EINVAL; in mxs_dma_validate_chan()
48 return desc->address + offsetof(struct mxs_dma_desc, cmd); in mxs_dma_cmd_address()
57 * so it must be be viewed as immediately stale.
76 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); in mxs_dma_read_semaphore()
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|
| /openbmc/linux/Documentation/driver-api/usb/ |
| H A D | gadget.rst | 11 This document presents a Linux-USB "Gadget" kernel mode API, for use
17 - Supports USB 2.0, for high speed devices which can stream data at
20 - Handles devices with dozens of endpoints just as well as ones with
21 just two fixed-function ones. Gadget drivers can be written so
24 - Flexible enough to expose more complex USB device capabilities such
28 - USB "On-The-Go" (OTG) support, in conjunction with updates to the
29 Linux-USB host side.
31 - Sharing data structures and API models with the Linux-USB host side
32 API. This helps the OTG support, and looks forward to more-symmetric
36 - Minimalist, so it's easier to support new device controller hardware.
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|
| /openbmc/qemu/target/arm/ |
| H A D | cpregs.h | 18 * <http://www.gnu.org/licenses/gpl-2.0.html>
25 #include "target/arm/kvm-consts.h"
51 /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
86 * code will synchronize the CPU state before calling the hook so that it
91 * Flag: Writes to the sysreg might change the exception level - typically
92 * on older ARM chips. For those cases we need to re-read the new el when
110 * - UNDEF: discard the cpreg,
111 * - KEEP: retain the cpreg as is,
112 * - C_NZ: set const on the cpreg, but retain resetvalue,
113 * - else: set const on the cpreg, zero resetvalue, aka RES0.
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| /openbmc/linux/Documentation/arch/s390/ |
| H A D | vfio-ap.rst | 13 The AP adapter cards are exposed via the AP bus. The motivation for vfio-ap
32 CPU.
45 sub-directory::
76 significant bit, correspond to domains 0-255.
111 * NQAP: to enqueue an AP command-request message to a queue
112 * DQAP: to dequeue an AP command-reply message from a queue
132 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
137 corresponds to an AP queue index (APQI) from 0-255. If a bit is set, the
142 changed by an AP command-request message sent to a usage domain from the
144 0-255. If a bit is set, the corresponding domain can be modified by an AP
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|
| /openbmc/linux/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
26 2-3. [Un]populated Notification
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|
| /openbmc/linux/Documentation/gpu/ |
| H A D | i915.rst | 17 ------------------------
19 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
22 .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
25 .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
29 ------------------
31 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
34 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
37 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
40 .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
43 Intel GVT-g Guest Support(vGPU)
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| /openbmc/linux/drivers/pci/controller/ |
| H A D | pcie-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
273 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
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|