18  * <http://www.gnu.org/licenses/gpl-2.0.html>
25 #include "target/arm/kvm-consts.h"
51     /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
86      * code will synchronize the CPU state before calling the hook so that it
91      * Flag: Writes to the sysreg might change the exception level - typically
92      * on older ARM chips. For those cases we need to re-read the new el when
110      *   - UNDEF: discard the cpreg,
111      *   -  KEEP: retain the cpreg as is,
112      *   -  C_NZ: set const on the cpreg, but retain resetvalue,
113      *   -  else: set const on the cpreg, zero resetvalue, aka RES0.
144  *  non-secure/secure bank (AArch32 only)
164  * To enable banking of coprocessor registers depending on ns-bit we
165  * add a bit to distinguish between secure and non-secure cpregs in the
199          * KVM is always non-secure so add the NS flag on AArch32 register  in kvm_to_cpreg_id()
248  * The existence of both or neither secure and non-secure flags indicates that
249  * the register has both a secure and non-secure hash entry.  A single one of
254  * or non-secure.
259     ARM_CP_SECSTATE_NS =  (1 << 1), /* bit[1]: Non-secure state register */
264  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
270  * (ie anything visible in PL2 is visible in S-PL1, some things are only
271  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
291      * For user-mode some registers are accessible to EL0 via a kernel
292      * trap-and-emulate ABI. In this case we define the read permissions
331      * Note that this is not a catch-all case -- the set of cases which may
399 /* 51-53: RES0 */
402 /* 56-63: RES0 */
624 /* Which fine-grained trap bit register to check, if any */
651      * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
669      * it as trap-on-writes.
844      * 'wildcard' field -- any value of that field in the MRC/MCR insn
851      * For AArch64-visible registers, opc0 is also used.
853      * way to distinguish (for KVM's benefit) guest-visible system registers
874      * Which fine-grained trap register bit to check, if any. This
893      * fieldoffset is non-zero, the reset value of the register.
905      * Offsets of the secure and non-secure fields in CPUARMState for the
941      * readfn and it has side effects (for instance clear-on-read bits).
948      * writefn and it masks out "unwritable" bits or has write-one-to-clear
961      * For ARMv8.1-VHE register aliases, we overwrite the read/write
979     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
981     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
983 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
986 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)  in define_one_arm_cp_reg()  argument
988     define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);  in define_one_arm_cp_reg()
991 void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
994 #define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE)               \  argument
997         define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE,           \
1001 #define define_arm_cp_regs(CPU, REGS) \  argument
1002     define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
1007  * Definition of an ARM co-processor register as viewed from
1009  * registers to userspace when emulating the Linux AArch64 CPU
1038 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1041 /* CPReadFn that can be used for read-as-zero behaviour */
1044 /* CPWriteFn that just writes the value to ri->fieldoffset */
1054  * Return true if this reginfo struct's field in the cpu state struct
1059     return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);  in cpreg_field_is_64bit()
1065     return (ri->access >> ((current_el * 2) + isread)) & 1;  in cp_access_ok()
1090     return ri->state == ARM_CP_STATE_AA64 &&  in arm_cpreg_in_idspace()
1091         arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2,  in arm_cpreg_in_idspace()
1092                                       ri->crn, ri->crm);  in arm_cpreg_in_idspace()
1096 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }  in define_cortex_a72_a57_a53_cp_reginfo()  argument
1098 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
1134     return ri->opc1 == 4 || ri->opc1 == 5;  in arm_cpreg_traps_in_nv()