1 // SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
22 #include <asm/mach-imx/regs-apbh.h>
34 		return -EINVAL;  in mxs_dma_validate_chan()
37 	if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))  in mxs_dma_validate_chan()
38 		return -EINVAL;  in mxs_dma_validate_chan()
48 	return desc->address + offsetof(struct mxs_dma_desc, cmd);  in mxs_dma_cmd_address()
57  * so it must be be viewed as immediately stale.
76 	tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_read_semaphore()
123 	if (pchan->pending_num == 0) {  in mxs_dma_enable()
124 		pchan->flags |= MXS_DMA_FLAGS_BUSY;  in mxs_dma_enable()
128 	pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);  in mxs_dma_enable()
130 		return -EFAULT;  in mxs_dma_enable()
132 	if (pchan->flags & MXS_DMA_FLAGS_BUSY) {  in mxs_dma_enable()
133 		if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))  in mxs_dma_enable()
141 			pdesc = list_entry(pdesc->node.next,  in mxs_dma_enable()
144 				&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
146 		writel(pchan->pending_num,  in mxs_dma_enable()
147 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
148 		pchan->active_num += pchan->pending_num;  in mxs_dma_enable()
149 		pchan->pending_num = 0;  in mxs_dma_enable()
151 		pchan->active_num += pchan->pending_num;  in mxs_dma_enable()
152 		pchan->pending_num = 0;  in mxs_dma_enable()
154 			&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
155 		writel(pchan->active_num,  in mxs_dma_enable()
156 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
158 			&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_enable()
161 	pchan->flags |= MXS_DMA_FLAGS_BUSY;  in mxs_dma_enable()
192 	if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))  in mxs_dma_disable()
193 		return -EINVAL;  in mxs_dma_disable()
196 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_disable()
198 	pchan->flags &= ~MXS_DMA_FLAGS_BUSY;  in mxs_dma_disable()
199 	pchan->active_num = 0;  in mxs_dma_disable()
200 	pchan->pending_num = 0;  in mxs_dma_disable()
201 	list_splice_init(&pchan->active, &pchan->done);  in mxs_dma_disable()
215 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_reset()
218 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);  in mxs_dma_reset()
234  * This function enables the given DMA channel to interrupt the CPU.
248 			&apbh_regs->hw_apbh_ctrl1_set);  in mxs_dma_enable_irq()
251 			&apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_enable_irq()
272 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_ack_irq()
273 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);  in mxs_dma_ack_irq()
286 		return -EINVAL;  in mxs_dma_request()
289 	if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)  in mxs_dma_request()
290 		return -ENODEV;  in mxs_dma_request()
292 	if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)  in mxs_dma_request()
293 		return -EBUSY;  in mxs_dma_request()
295 	pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;  in mxs_dma_request()
296 	pchan->active_num = 0;  in mxs_dma_request()
297 	pchan->pending_num = 0;  in mxs_dma_request()
299 	INIT_LIST_HEAD(&pchan->active);  in mxs_dma_request()
300 	INIT_LIST_HEAD(&pchan->done);  in mxs_dma_request()
324 	if (pchan->flags & MXS_DMA_FLAGS_BUSY)  in mxs_dma_release()
325 		return -EBUSY;  in mxs_dma_release()
327 	pchan->dev = 0;  in mxs_dma_release()
328 	pchan->active_num = 0;  in mxs_dma_release()
329 	pchan->pending_num = 0;  in mxs_dma_release()
330 	pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;  in mxs_dma_release()
350 	pdesc->address = (dma_addr_t)pdesc;  in mxs_dma_desc_alloc()
417 	pdesc->cmd.next = mxs_dma_cmd_address(pdesc);  in mxs_dma_desc_append()
418 	pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;  in mxs_dma_desc_append()
420 	if (!list_empty(&pchan->active)) {  in mxs_dma_desc_append()
421 		last = list_entry(pchan->active.prev, struct mxs_dma_desc,  in mxs_dma_desc_append()
424 		pdesc->flags &= ~MXS_DMA_DESC_FIRST;  in mxs_dma_desc_append()
425 		last->flags &= ~MXS_DMA_DESC_LAST;  in mxs_dma_desc_append()
427 		last->cmd.next = mxs_dma_cmd_address(pdesc);  in mxs_dma_desc_append()
428 		last->cmd.data |= MXS_DMA_DESC_CHAIN;  in mxs_dma_desc_append()
432 	pdesc->flags |= MXS_DMA_DESC_READY;  in mxs_dma_desc_append()
433 	if (pdesc->flags & MXS_DMA_DESC_FIRST)  in mxs_dma_desc_append()
434 		pchan->pending_num++;  in mxs_dma_desc_append()
435 	list_add_tail(&pdesc->node, &pchan->active);  in mxs_dma_desc_append()
446  * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
471 	if (sem == pchan->active_num)  in mxs_dma_finish()
474 	list_for_each_safe(p, q, &pchan->active) {  in mxs_dma_finish()
475 		if ((pchan->active_num) <= sem)  in mxs_dma_finish()
479 		pdesc->flags &= ~MXS_DMA_DESC_READY;  in mxs_dma_finish()
484 			list_move_tail(p, &pchan->done);  in mxs_dma_finish()
486 		if (pdesc->flags & MXS_DMA_DESC_LAST)  in mxs_dma_finish()
487 			pchan->active_num--;  in mxs_dma_finish()
491 		pchan->flags &= ~MXS_DMA_FLAGS_BUSY;  in mxs_dma_finish()
509 	if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,  in mxs_dma_wait_complete()
511 		ret = -ETIMEDOUT;  in mxs_dma_wait_complete()
549  *	 for the LCD driver in Smart-LCD mode. It allows
562 		&apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);  in mxs_dma_circ_start()
563 	writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);  in mxs_dma_circ_start()
565 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_circ_start()
576 	mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);  in mxs_dma_init()
580 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_init()
583 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_init()
588 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_init()
591 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_init()
601 	pchan->flags = MXS_DMA_FLAGS_VALID;  in mxs_dma_init_channel()