| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | prcm-regs.c | 93 /* cm2.ckgen */
134 /* cm2.core */
179 /* cm2.ivahd */
184 /* cm2.cam */
189 /* cm2.dss */
193 /* cm2.sgx */
197 /* cm2.l3init */
211 /* cm2.l4per */
550 /* cm2.ckgen */
595 /* cm2.core */
[all …]
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | cm2_44xx.h | 3 * OMAP44xx CM2 instance offset macros
25 /* CM2 base address */
31 /* CM2 instances */
44 /* CM2 clockdomain register offsets (from instance start) */
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| H A D | cm2_54xx.h | 3 * OMAP54xx CM2 instance offset macros
21 /* CM2 base address */
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| H A D | cm2_7xx.h | 3 * DRA7xx CM2 instance offset macros
22 /* CM2 base address */
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| H A D | cm44xx.h | 10 * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains
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| H A D | prcm44xx.h | 11 * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
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| H A D | cm_common.c | 34 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
280 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
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| H A D | cminst44xx.c | 11 * or CM2 hardware modules. For example, the EMU_CM CM instance is in
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | prcm-regs.c | 90 /* cm2.ckgen */
133 /* cm2.core */
177 /* cm2.ivahd */
181 /* cm2.cam */
186 /* cm2.dss */
190 /* cm2.sgx */
194 /* cm2.l3init */
206 /* cm2.l4per */
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| /openbmc/u-boot/arch/arm/include/asm/ |
| H A D | omap_common.h | 99 /* cm2.ckgen */
150 /* cm2.core */
195 /* cm2.ivahd */
200 /* cm2.cam */
211 /* cm2.dss */
215 /* cm2.sgx */
219 /* cm2.l3init */
222 /* cm2.l3init */
240 /* cm2.l4per */
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| /openbmc/linux/Documentation/devicetree/bindings/arm/omap/ |
| H A D | prcm.txt | 19 "ti,omap4-cm2"
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| /openbmc/linux/Documentation/devicetree/bindings/cache/ |
| H A D | baikal,bt1-l2-ctl.yaml | 15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | ti-clkctrl.txt | 32 &cm2 {
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3566-soquartz-blade.dts | 86 * i2c4 is exposed on CM2 / Module1B - to PI40
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| H A D | rk3566-soquartz-cm4.dts | 90 * i2c4 is exposed on CM2 / Module1B - to PI40
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| H A D | rk3566-soquartz-model-a.dts | 113 * i2c4 is exposed on CM2 / Module1B - to PI40
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| H A D | rk3566-soquartz.dtsi | 443 * i2c4 is exposed on CM2 / Module1B
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| /openbmc/linux/drivers/memory/ |
| H A D | Kconfig | 68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
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| H A D | bt1-l2-ctl.c | 8 * Baikal-T1 CM2 L2-cache Control Block driver.
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| /openbmc/linux/drivers/bus/ |
| H A D | bt1-axi.c | 217 * Performing unaligned read from the memory will cause the CM2 bus in inject_error_store()
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| /openbmc/linux/arch/mips/kernel/ |
| H A D | mips-cm.c | 392 if (revision < CM_REV_CM3) { /* CM2 */ in mips_cm_error_report()
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| /openbmc/linux/Documentation/input/joydev/ |
| H A D | joystick.rst | 485 but in the future, Logitech CyberMan (the original one, not CM2) could be
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap4-l4.dtsi | 122 cm2: cm2@0 { label
123 compatible = "ti,omap4-cm2", "simple-bus";
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| H A D | omap44xx-clocks.dtsi | 1202 &cm2 {
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| /openbmc/linux/arch/mips/ |
| H A D | Kconfig | 1525 level features like up to six P5600 calculation cores, CM2 with L2
|