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/openbmc/u-boot/board/micronas/vct/vctv/
H A Dreg_ebi.h16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/openbmc/u-boot/board/micronas/vct/vcth2/
H A Dreg_ebi.h16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
22 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
24 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
26 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
28 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
30 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
32 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
34 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/openbmc/u-boot/board/micronas/vct/vcth/
H A Dreg_ebi.h16 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
18 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
20 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
22 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
24 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
26 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
28 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
30 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
32 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
34 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
[all …]
H A Dreg_fwsram.h21 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
23 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
25 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
27 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
29 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
31 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
33 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
35 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
37 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) argument
39 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) argument
[all …]
H A Dreg_scc.h56 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) argument
58 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) argument
60 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) argument
62 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) argument
64 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) argument
66 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) argument
68 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) argument
70 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) argument
72 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) argument
74 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) argument
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/lmbench/lmbench/
H A D0001-scripts-build-Fix-the-tests-to-build-with-clang15.patch14 @@ -21,7 +21,7 @@ trap 'rm -f ${BASE}$$.s ${BASE}$$.c ${BA
18 -echo "main(int ac, char *av[]) { int i; }" > ${BASE}$$.c
19 +echo "int main(int ac, char *av[]) { int i; }" > ${BASE}$$.c
20 if ${CC} ${CFLAGS} -o ${BASE}$$ ${BASE}$$.c 1>${NULL} 2>${NULL}
26 echo "#include <stdlib.h>" > ${BASE}$$.c
27 - echo "main(int ac, char *av[])" >> ${BASE}$$.c
28 + echo "int main(int ac, char *av[])" >> ${BASE}$$.c
29 echo "{ long* p = (long*)malloc(sizeof(long));" >> ${BASE}$$.c
30 echo "*p = 0; exit((int)*p); }" >> ${BASE}$$.c
31 ${CC} ${CFLAGS} +DD64 -o ${BASE}$$ ${BASE}$$.c 1>${NULL} 2>${NULL} \
[all …]
/openbmc/qemu/hw/m68k/
H A Dbootinfo.h15 #define BOOTINFO0(base, id) \ argument
17 stw_be_p(base, id); \
18 base += 2; \
19 stw_be_p(base, sizeof(struct bi_record)); \
20 base += 2; \
23 #define BOOTINFO1(base, id, value) \ argument
25 stw_be_p(base, id); \
26 base += 2; \
27 stw_be_p(base, sizeof(struct bi_record) + 4); \
28 base += 2; \
[all …]
/openbmc/openbmc/poky/meta/recipes-core/packagegroups/
H A Dpackagegroup-base.bb11 packagegroup-base \
12 packagegroup-base-extended \
13 packagegroup-distro-base \
14 packagegroup-machine-base \
16 ${@bb.utils.contains("MACHINE_FEATURES", "acpi", "packagegroup-base-acpi", "",d)} \
17 ${@bb.utils.contains("MACHINE_FEATURES", "alsa", "packagegroup-base-alsa", "", d)} \
18 ${@bb.utils.contains("MACHINE_FEATURES", "ext2", "packagegroup-base-ext2", "", d)} \
19 ${@bb.utils.contains("MACHINE_FEATURES", "vfat", "packagegroup-base-vfat", "", d)} \
20 … ${@bb.utils.contains("MACHINE_FEATURES", "keyboard", "packagegroup-base-keyboard", "", d)} \
21 ${@bb.utils.contains("MACHINE_FEATURES", "pci", "packagegroup-base-pci", "",d)} \
[all …]
/openbmc/openbmc/poky/meta/recipes-core/musl/
H A Dmusl-locales_git.bb31 LICENSE:locale-base-cs-cz = "MIT"
32 LICENSE:locale-base-de-ch = "MIT"
33 LICENSE:locale-base-de-de = "MIT"
34 LICENSE:locale-base-en-gb = "MIT"
35 LICENSE:locale-base-en-us = "MIT"
36 LICENSE:locale-base-es-es = "MIT"
37 LICENSE:locale-base-fi-fi = "MIT"
38 LICENSE:locale-base-fr-ca = "MIT"
39 LICENSE:locale-base-fr-fr = "MIT"
40 LICENSE:locale-base-it-it = "MIT"
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dcpu.h11 /* AHB physical base addresses */
12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
16 #define DMA_BASE 0x31000000 /* DMA controller registers base */
17 #define USB_BASE 0x31020000 /* USB registers base */
18 #define LCD_BASE 0x31040000 /* LCD registers base */
19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
[all …]
/openbmc/u-boot/lib/zlib/
H A Dadler32.c11 #define BASE 65521UL /* largest prime smaller than 65536 */ macro
13 /* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
25 if (a >= (BASE << 16)) a -= (BASE << 16); \
26 if (a >= (BASE << 15)) a -= (BASE << 15); \
27 if (a >= (BASE << 14)) a -= (BASE << 14); \
28 if (a >= (BASE << 13)) a -= (BASE << 13); \
29 if (a >= (BASE << 12)) a -= (BASE << 12); \
30 if (a >= (BASE << 11)) a -= (BASE << 11); \
31 if (a >= (BASE << 10)) a -= (BASE << 10); \
32 if (a >= (BASE << 9)) a -= (BASE << 9); \
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c34 void __iomem *base; in uniphier_ld20_sscpll_init() local
37 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_init()
38 if (!base) in uniphier_ld20_sscpll_init()
42 tmp = readl(base); /* SSCPLLCTRL */ in uniphier_ld20_sscpll_init()
47 writel(tmp, base); in uniphier_ld20_sscpll_init()
49 tmp = readl(base + 4); in uniphier_ld20_sscpll_init()
54 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
59 tmp = readl(base + 4); /* SSCPLLCTRL2 */ in uniphier_ld20_sscpll_init()
61 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
63 iounmap(base); in uniphier_ld20_sscpll_init()
[all …]
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3.c24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy() argument
28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
32 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
37 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
39 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
[all …]
/openbmc/openbmc/poky/meta/recipes-multimedia/gstreamer/
H A Dgstreamer1.0-meta-base.bb12 DEPENDS = "gstreamer1.0 gstreamer1.0-plugins-base gstreamer1.0-plugins-good ${DEPENDS_UGLY} ${DEPEN…
15 gstreamer1.0-meta-base \
16 gstreamer1.0-meta-x11-base \
21 ALLOW_EMPTY:gstreamer1.0-meta-base = "1"
22 ALLOW_EMPTY:gstreamer1.0-meta-x11-base = "1"
27 RDEPENDS:gstreamer1.0-meta-base = "\
28 ${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'gstreamer1.0-meta-x11-base', '', d)} \
30 gstreamer1.0-plugins-base-playback \
31 gstreamer1.0-plugins-base-gio \
32 ${@bb.utils.contains('COMBINED_FEATURES', 'alsa', 'gstreamer1.0-plugins-base-alsa', '',d)} \
[all …]
/openbmc/sdeventplus/src/sdeventplus/source/
H A Dbase.cpp3 #include <sdeventplus/source/base.hpp>
14 sd_event_source* Base::get() const in get()
19 const Event& Base::get_event() const in get_event()
24 const char* Base::get_description() const in get_description()
33 void Base::set_description(const char* description) const in set_description()
40 void Base::set_prepare(Callback&& callback) in set_prepare()
56 bool Base::get_pending() const in get_pending()
63 int64_t Base::get_priority() const in get_priority()
72 void Base::set_priority(int64_t priority) const in set_priority()
79 Enabled Base::get_enabled() const in get_enabled()
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv8m-base.inc2 # Defaults for ARMv8-m.base
4 DEFAULTTUNE ?= "armv8m-base"
6 TUNEVALID[armv8m-base] = "Enable instructions for ARMv8-m.base"
7 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8m-base', ' -march=armv8-m.base', …
8 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8m-base', 'armv8m-base:', '', d)}"
10 TUNECONFLICTS[armv8m-base] = "armv4 armv5 armv6 armv7a"
14 AVAILTUNES += "armv8m-base"
15 ARMPKGARCH:tune-armv8m-base = "armv8m-base"
16 TUNE_FEATURES:tune-armv8m-base = "armv8m-base"
17 PACKAGE_EXTRA_ARCHS:tune-armv8m-base = "armv8m-base"
/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dbsec.c16 /* BSEC REGISTER OFFSET (base relative) */
54 * @base: base address of bsec IP
58 static u32 bsec_check_error(u32 base, u32 otp) in bsec_check_error() argument
66 if (readl(base + BSEC_DISTURBED_OFF + bank) & bit) in bsec_check_error()
68 else if (readl(base + BSEC_ERROR_OFF + bank) & bit) in bsec_check_error()
93 * @base: base address of bsec IP
97 static bool bsec_read_SR_lock(u32 base, u32 otp) in bsec_read_SR_lock() argument
99 return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); in bsec_read_SR_lock()
104 * @base: base address of bsec IP
108 static bool bsec_read_SP_lock(u32 base, u32 otp) in bsec_read_SP_lock() argument
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_mvebu_a3700.c12 void __iomem *base; member
36 void __iomem *base = plat->base; in mvebu_serial_putc() local
38 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) in mvebu_serial_putc()
41 writel(ch, base + UART_TX_REG); in mvebu_serial_putc()
49 void __iomem *base = plat->base; in mvebu_serial_getc() local
51 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)) in mvebu_serial_getc()
54 return readl(base + UART_RX_REG) & 0xff; in mvebu_serial_getc()
60 void __iomem *base = plat->base; in mvebu_serial_pending() local
62 if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY) in mvebu_serial_pending()
71 void __iomem *base = plat->base; in mvebu_serial_setbrg() local
[all …]
/openbmc/u-boot/lib/
H A Dlmb.c24 debug(" memory.reg[0x%lx].base = 0x%llx\n", i, in lmb_dump_all()
25 (unsigned long long)lmb->memory.region[i].base); in lmb_dump_all()
35 debug(" reserved.reg[0x%lx].base = 0x%llx\n", i, in lmb_dump_all()
36 (unsigned long long)lmb->reserved.region[i].base); in lmb_dump_all()
66 phys_addr_t base1 = rgn->region[r1].base; in lmb_regions_adjacent()
68 phys_addr_t base2 = rgn->region[r2].base; in lmb_regions_adjacent()
79 rgn->region[i].base = rgn->region[i + 1].base; in lmb_remove_region()
85 /* Assumption: base addr of region 1 < base addr of region 2 */
133 void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, in lmb_init_and_reserve_range() argument
137 lmb_add(lmb, base, size); in lmb_init_and_reserve_range()
[all …]
/openbmc/qemu/disas/
H A Dalpha.c65 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
255 The information for the base instruction set was compiled from the
638 #define BASE AXP_OPCODE_BASE macro
710 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
711 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
712 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
713 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
714 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
715 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
716 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
[all …]
/openbmc/u-boot/drivers/i2c/
H A Dmv_i2c.c68 static void i2c_reset(struct mv_i2c *base) in i2c_reset() argument
73 icr_mode = readl(&base->icr) & ICR_MODE_MASK; in i2c_reset()
74 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
75 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ in i2c_reset()
77 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
81 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ in i2c_reset()
83 writel(I2C_ICR_INIT | icr_mode, &base->icr); in i2c_reset()
84 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ in i2c_reset()
85 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ in i2c_reset()
95 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask, in i2c_isr_set_cleared() argument
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_mmu.S6 #define BASE 0x20000000 macro
35 movi a2, BASE | XCHAL_SPANNING_WAY
48 movi a3, BASE + 0x01200004 /* VPN */
54 movi a3, BASE + 0x01000001
63 movi a3, BASE + 0x01234567
66 movi a3, BASE + 0x01234014
68 movi a3, BASE + 0x0123400c
73 movi a3, BASE + 0x01234567
87 movi a3, BASE + 0x00100000
101 movi a3, BASE + 0x00100000
[all …]
/openbmc/telemetry/tests/src/
H A Dtest_path_append.cpp19 Values(std::make_tuple(object_path("/Base/Path"), "one",
20 object_path("/Base/Path/one")),
21 std::make_tuple(object_path("/Base/Path"), "one/two",
22 object_path("/Base/Path/one/two")),
23 std::make_tuple(object_path("/Base/Path"), "one/two/foobar",
24 object_path("/Base/Path/one/two/foobar")),
25 std::make_tuple(object_path("/Base/Path/"), "one",
26 object_path("/Base/Path/one")),
27 std::make_tuple(object_path("/Base/Path/"), "one/two",
28 object_path("/Base/Path/one/two")),
[all …]
/openbmc/u-boot/drivers/virtio/
H A Dvirtio_mmio.c23 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; in virtio_mmio_get_config() local
33 ptr[i] = readb(base + offset + i); in virtio_mmio_get_config()
40 b = readb(base + offset); in virtio_mmio_get_config()
44 w = cpu_to_le16(readw(base + offset)); in virtio_mmio_get_config()
48 l = cpu_to_le32(readl(base + offset)); in virtio_mmio_get_config()
52 l = cpu_to_le32(readl(base + offset)); in virtio_mmio_get_config()
54 l = cpu_to_le32(readl(base + offset + sizeof(l))); in virtio_mmio_get_config()
68 void __iomem *base = priv->base + VIRTIO_MMIO_CONFIG; in virtio_mmio_set_config() local
78 writeb(ptr[i], base + offset + i); in virtio_mmio_set_config()
86 writeb(b, base + offset); in virtio_mmio_set_config()
[all …]
/openbmc/phosphor-webui/app/common/styles/base/
H A Dcolors.scss1 // Base colors
37 $base-01--01: $color--blue-100;
38 $base-01--02: $color--blue-50;
39 $base-01--03: $color--blue-40;
40 $base-01--04: $color--blue-30;
41 $base-01--05: $color--blue-20;
43 $base-02--01: $color--grey-100;
44 $base-02--02: $color--grey-80;
45 $base-02--03: $color--grey-60;
46 $base-02--04: $color--grey-40;
[all …]

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