1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 4 * 5 * Copyright (C) 2006 Micronas GmbH 6 */ 7 8 /* 9 * Premium & Platinum register addresses/definitions seem to be 10 * identical, so we only need to use one file for both platforms. 11 */ 12 13 #ifndef _REG_FWSRAM_H_ 14 #define _REG_FWSRAM_H_ 15 16 #define FWSRAM_BASE 0x00030000 17 18 /* Relative offsets of the register adresses */ 19 20 #define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 21 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) 22 #define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 23 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) 24 #define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 25 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) 26 #define FWSRAM_TOP_CID1_H_OFFS 0x0000200C 27 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) 28 #define FWSRAM_TOP_CID1_L_OFFS 0x00002010 29 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) 30 #define FWSRAM_TOP_CID2_H_OFFS 0x00002014 31 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) 32 #define FWSRAM_TOP_CID2_L_OFFS 0x00002018 33 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) 34 #define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C 35 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) 36 #define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 37 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) 38 #define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 39 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) 40 #define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 41 #define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) 42 #define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C 43 #define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) 44 #define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 45 #define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) 46 #define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 47 #define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) 48 #define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 49 #define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) 50 #define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C 51 #define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) 52 #define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 53 #define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) 54 #define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 55 #define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) 56 #define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 57 #define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) 58 59 #endif 60